臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Showing items 26-31 of 31 (1 Page(s) Totally)
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Institution	Date	Title	Author
國立中山大學	2000-06	A practical load-optimized VCO design for low-jitter 5V 500 MHz digital phase-locked loop	C.C. Wang;Y.T. Chien;Y.P. Chen
國立中山大學	2000-05	Design of an inter-plane circuit for clocked PLAs	C.C. Wang;Y.T. Chien;Y.P. Chen
國立中山大學	2000	Design of an inner-product processor for hardware realization of multi-valued exponential bidirectional associative memory	C.C. Wang;C.J. Huang;Y.P. Chen
國立中山大學	2000	A practical load-optimized VCO design for low-jitter 5V 500 MHz digital phase-locked loop	C.C. Wang;Y.T. Chien;Y.P. Chen
國立中山大學	1999-06	A practical load-optimized VCO design for low-jitter 5V 500 MHz digital phase-locked loop	C.C. Wang;Y.T. Chien;Y.P. Chen
國立中山大學	1999-05	Power-saving fast half-swing inter-plane circuit for clocked PLAs	C.C. Wang;Y.T. Chien;Y.P. Chen

Showing items 26-31 of 31 (1 Page(s) Totally)
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