臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Institution	Date	Title	Author
臺大學術典藏	2020-10-07T01:24:52Z	Using ultrasound CBE imaging without echo shift compensation for temperature estimation	W-S Chen; H-L Liu; Y-C Shu; Y-T Chien; P-H Tsui; HAO-LI LIU; 劉浩澧; W-S Chen; H-L Liu; Y-C Shu; HAO-LI LIU; P-H Tsui; Y-T Chien
臺大學術典藏	2012	Ultrasound temperature estimation based on probability variation of backscatter data	P-H Tsui; Y-C Shu; W-S Chen; H-L Liu; HAO-LI LIU; Y-T Chien; I-T Hsiao; W-S Chen; H-L Liu; P-H Tsui; Y-C Shu; I-T Hsiao; Y-T Chien; 劉浩澧; HAO-LI LIU
國立中山大學	2002-06	Design of an inter-plane circuit for clocked PLAs	C.C. Wang;Y.H. Hsueh;Y.T. Chien;Y.P. Chen
國立中山大學	2002	Design of an inter-plane circuit for clocked PLAs	C.C. Wang;Y.H. Hsueh;Y.T. Chien;Y.P. Chen
國立中山大學	2001-09	Fast half-swing inter-plane circuits for clocked NOR-NOR PLAs	C.C. Wang;C.C. Chiu;Y.T. Chien
國立中山大學	2001-03	Pattern recognition by high-capacity polynomial bidirectional hetero-associative network	C.C. Wang;C.F. Tsai;Y.T. Chien
國立中山大學	2001	Pattern recognition by high-capacity polynomial bidirectional hetero-associative network	C.C. Wang;C.F. Tsai;Y.T. Chien
國立中山大學	2000-06	A practical load-optimized VCO design for low-jitter 5V 500 MHz digital phase-locked loop	C.C. Wang;Y.T. Chien;Y.P. Chen
國立中山大學	2000-05	Design of an inter-plane circuit for clocked PLAs	C.C. Wang;Y.T. Chien;Y.P. Chen
國立中山大學	2000	A practical load-optimized VCO design for low-jitter 5V 500 MHz digital phase-locked loop	C.C. Wang;Y.T. Chien;Y.P. Chen
國立中山大學	1999-06	A practical load-optimized VCO design for low-jitter 5V 500 MHz digital phase-locked loop	C.C. Wang;Y.T. Chien;Y.P. Chen
國立中山大學	1999-05	Power-saving fast half-swing inter-plane circuit for clocked PLAs	C.C. Wang;Y.T. Chien;Y.P. Chen

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