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Showing items 1-9 of 9 (1 Page(s) Totally)
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| 國立交通大學 |
2017-04-21T06:48:17Z |
An Efficient BCH Decoder with 124-bit Correctability for Multi-Channel SSD Applications
|
Tsai, Hung-Yuan; Yang, Chi-Heng; Chang, Hsie-Chia |
| 國立交通大學 |
2015-12-02T02:59:09Z |
An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability
|
Yang, Chi-Heng; Lin, Yi-Min; Chang, Hsie-Chia; Lee, Chen-Yi |
| 國立交通大學 |
2015-07-21T08:31:07Z |
An Area-Efficient BCH Codec with Echelon Scheduling for NAND Flash Applications
|
Yang, Chi-Heng; Chen, Yi-Hsun; Chang, Hsie-Chia |
| 國立交通大學 |
2014-12-16T06:15:19Z |
APPARATUS AND METHOD OF PROCESSING CYCLIC CODES
|
LIN Yi-Min; YANG Chi-Heng; CHANG Hsie-Chia; LEE Chen-Yi |
| 國立交通大學 |
2014-12-16T06:14:49Z |
FULLY PARALLEL ENCODING METHOD AND FULLY PARALLEL DECODING METHOD OF MEMORY SYSTEM
|
CHU Chia-Ching; LIN Yi-Min; YANG Chi-Heng; CHANG Hsie-Chia |
| 國立交通大學 |
2014-12-16T06:13:55Z |
Apparatus and method of processing polynomials
|
Lin Yi-Min; Yang Chi-Heng; Chang Hsie-Chia; Lee Chen-Yi |
| 國立交通大學 |
2014-12-12T02:45:41Z |
應用於NAND型快閃記憶體系統之BCH編解碼器之研究
|
楊其衡; Yang, Chi-Heng; 張錫嘉; Chang, Hsie-Chia |
| 國立交通大學 |
2014-12-08T15:29:04Z |
A Fully Parallel BCH Codec with Double Error Correcting Capability for NOR Flash Applications
|
Chu, Chia-Ching; Lin, Yi-Min; Yang, Chi-Heng; Chang, Hsie-Chia |
| 國立交通大學 |
2014-12-08T15:20:48Z |
A MPCN-Based Parallel Architecture in BCH Decoders for NAND Flash Memory Devices
|
Lin, Yi-Min; Yang, Chi-Heng; Hsu, Chih-Hsiang; Chang, Hsie-Chia; Lee, Chen-Yi |
Showing items 1-9 of 9 (1 Page(s) Totally)
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