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"yang chia hsiang"的相關文件
顯示項目 6-30 / 71 (共3頁)
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| 國立交通大學 |
2020-01-02T00:04:19Z |
Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem
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Qian, Xin-Hong; Wu, Yi-Chung; Yang, Tzu-Yi; Cheng, Cheng-Hsiang; Chu, Hsing-Chien; Cheng, Wan-Hsueh; Yen, Ting-Yang; Lin, Tzu-Han; Lin, Yung-Jen; Lee, Yu-Chi; Chang, Jia-Heng; Lin, Shih-Ting; Li, Shang-Hsuan; Wu, Tsung-Chen; Huang, Chien-Chang; Wang, Sung-Hao; Lee, Chia-Fone; Yang, Chia-Hsiang; Hung, Chung-Chih; Chi, Tai-Shih; Liu, Chien-Hao; Ker, Ming-Dou; Wu, Chung-Yu |
| 國立交通大學 |
2019-12-13T01:12:51Z |
A 2.17mW Acoustic DSP Processor with CNN-FFT Accelerators for Intelligent Hearing Aided Devices
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Lee, Yu-Chi; Chi, Tai-Shih; Yang, Chia-Hsiang |
| 國立交通大學 |
2019-09-02T07:45:41Z |
Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs
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Wang, Yu-Zhe; Wu, Jingjie; Chen, Shi-Hao; Chao, Mango Chia-Tso; Yang, Chia-Hsiang |
| 國立交通大學 |
2019-04-02T06:04:52Z |
Power and Area Reduction in Multi-Stage Addition Using Operand Segmentation
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Chan, Ching-Da; Liu, Wei-Chang; Yang, Chia-Hsiang; Jou, Shyh-Jye |
| 國立交通大學 |
2019-04-02T06:04:27Z |
A 2x2-16x16 Reconfigurable GGMD Processor for MIMO Communication Systems
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Chiang, Chih-Hsuan; Huang, Shuo-An; Chen, Chiao-En; Yang, Chia-Hsiang |
| 國立交通大學 |
2019-04-02T06:00:43Z |
A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip
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Chou, Ting-I; Chang, Kwuang-Han; Jhang, Jia-Yin; Chiu, Shih-Wen; Wang, Guoxing; Yang, Chia-Hsiang; Chiueh, Herming; Chen, Hsin; Hsieh, Chih-Cheng; Chang, Meng-Fan; Tang, Kea-Tiong |
| 國立交通大學 |
2019-04-02T06:00:29Z |
A Hardware-Scalable DSP Architecture for Beam Selection in mm-Wave MU-MIMO Systems
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Yeh, Chun-Yu; Chu, Ting-Chung; Chen, Chiao-En; Yang, Chia-Hsiang |
| 國立交通大學 |
2019-04-02T06:00:26Z |
Iterative Inter-Cell Interference Cancellation Receiver for LDPC-Coded MIMO Systems
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Sun, Wei-Cheng; Chen, Yan-Tong; Yang, Chia-Hsiang; Ueng, Yeong-Luh |
| 國立交通大學 |
2019-04-02T06:00:26Z |
An Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MU-MIMO Systems
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Chen, Yan-Tong; Sun, Wei-Cheng; Cheng, Chung-Chao; Tsai, Tsung-Lin; Ueng, Yeong-Luh; Yang, Chia-Hsiang |
| 國立交通大學 |
2019-04-02T05:59:57Z |
A 135-mW Fully Integrated Data Processor for Next-Generation Sequencing
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Wu, Yi-Chung; Chang, Chia-Hua; Hung, Jui-Hung; Yang, Chia-Hsiang |
| 國立交通大學 |
2018-08-21T05:57:15Z |
A 501mW 7.61Gb/s Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MIMO Systems
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Chen, Yan-Tong; Cheng, Chung-Chao; Tsai, Tsung-Lin; Sun, Wei-Cheng; Ueng, Yeong-Luh; Yang, Chia-Hsiang |
| 國立交通大學 |
2018-08-21T05:57:14Z |
A Bone-Guided Cochlear Implant CMOS Microsystem Preserving Acoustic Hearing
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Qian, Xin-Hong; Wu, Yi-Chung; Yang, Tzu-Yi; Cheng, Cheng-Hsiang; Chu, Hsing-Chien; Cheng, Wan-Hsueh; Yen, Ting-Yang; Lin, Tsu-Han; Lin, Yung-Jen; Lee, Yu-Chi; Chang, Jia-Heng; Lin, Shih-Ting; Li, Shang-Hsuan; Wu, Tsung-Chen; Huang, Chien-Chang; Lee, Chia-Fone; Yang, Chia-Hsiang; Hung, Chung-Chih; Chi, Tai-Shih; Liu, Chien-Hao; Ker, Ming-Dou; Wu, Chung-Yu |
| 國立交通大學 |
2018-08-21T05:57:00Z |
Integration of Energy-Recycling Logic and Wireless Power Transfer for Ultra-Low-Power Implantables
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Lin, Hsin-Tzu; Wu, Yi-Chung; Hsieh, Ping-Hsuan; Yang, Chia-Hsiang |
| 國立交通大學 |
2018-08-21T05:56:47Z |
A 135mW Fully Integrated Data Processor for Next-Generation Sequencing
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Wu, Yi-Chung; Hung, Jui-Hung; Yang, Chia-Hsiang |
| 國立交通大學 |
2018-08-21T05:56:44Z |
Design of a 0.5V 1.68mW Nose-on-a-Chip for Rapid Screen of Chronic Obstructive Pulmonary Disease
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Chou, Ting-I; Chiu, Shih-Wen; Chang, Kwuang-Han; Chen, Yi-Ju; Tang, Chen-Ting; Shih, Chung-Hung; Hsieh, Chih-Cheng; Chang, Meng-Fan; Yang, Chia-Hsiang; Chiueh, Herming; Tang, Kea-Tiong |
| 國立交通大學 |
2018-08-21T05:56:32Z |
A Hardware-Efficient VLSI Architecture for Hybrid Sphere-MCMC Detection
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Yuan, Fang-Li; Yang, Chia-Hsiang; Markovic, Dejan |
| 國立交通大學 |
2018-01-24T07:42:55Z |
應用於超低功耗生醫植入式裝置之可回收能量邏輯及無線功率傳輸系統整合
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林欣慈; 楊家驤; Lin, Hsin-Tzu; Yang, Chia-Hsiang |
| 國立交通大學 |
2018-01-24T07:41:09Z |
應用於次世代定序之高速資料處理器設計與實現
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吳易忠; 楊家驤; Wu, Yi-Chung; Yang, Chia-Hsiang |
| 國立交通大學 |
2018-01-24T07:41:02Z |
應用於閉迴路神經調節系統具主動學習功能之機器學習處理器設計與實現
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黃碩安; 楊家驤; Huang, Shuo-An; Yang, Chia-Hsiang |
| 國立交通大學 |
2018-01-24T07:40:06Z |
應用於人工耳蝸具頻譜變化加強之語音訊號處理器設計與實現
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林詠仁; 楊家驤; Lin, Yung-Jen; Yang, Chia-Hsiang |
| 國立交通大學 |
2018-01-24T07:39:33Z |
具穿隧式電晶體與金氧半場效電晶體異質結構之超低能耗數位邏輯與非同步電路設計
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洪若翰; 楊家驤; Hung, Jo-Han; Yang, Chia-Hsiang |
| 國立交通大學 |
2018-01-24T07:39:03Z |
適用於多重天線系統之廣義幾何平均分解處理器
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江芷瑄; 楊家驤; Chiang, Chih-Hsuan; Yang, Chia-Hsiang |
| 國立交通大學 |
2018-01-24T07:39:00Z |
穿隧式電晶體與金氧半場效電晶體異質結構之非同步可程式邏輯陣列設計
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楊智文; 楊家驤; Yang, Chih-Wen; Yang, Chia-Hsiang |
| 國立交通大學 |
2018-01-24T07:39:00Z |
適用於巨量天線系統之整合訊息傳遞偵測與極化碼解碼接收機
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陳彥同; 楊家驤; Chen, Yan-Tong; Yang, Chia-Hsiang |
| 國立交通大學 |
2017-04-21T06:56:39Z |
sBWT: memory efficient implementation of the hardware-acceleration-friendly Schindler transform for the fast biological sequence mapping
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Chang, Chia-Hua; Chou, Min-Te; Wu, Yi-Chung; Hong, Ting-Wei; Li, Yun-Lung; Yang, Chia-Hsiang; Hung, Jui-Hung |
顯示項目 6-30 / 71 (共3頁)
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