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Taiwan Academic Institutional Repository >
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"yang chia lin"
Showing items 16-40 of 190 (8 Page(s) Totally)
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| 臺大學術典藏 |
2020-05-04T07:27:53Z |
Temporal floorplanning using the T-tree formulation.
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Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:53Z |
HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction.
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Yang, Chia-Lin; Lee, Chien-Hao; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:52Z |
Cache Leakage Management for Multi-programming Workloads.
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Chen, Chun-Yang; Yang, Chia-Lin; Hung, Shih-Hao; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:52Z |
Joint exploration of architectural and physical design spaces with thermal consideration.
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CHIA-LIN YANG; Chang, Yao-Wen; Yuh, Ping-Hung; Yang, Chia-Lin; Wu, Yen-Wei |
| 臺大學術典藏 |
2020-05-04T07:27:52Z |
Reconfigurable Platform for Content Science Research.
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Shih, Chi-Sheng; Yang, Chia-Lin; Ku, Mong-Kai; Kuo, Tei-Wei; Chien, Shao-Yi; Chang, Yao-Wen; Chen, Liang-Gee; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:52Z |
Temporal floorplanning using 3D-subTCG.
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Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; Chen, Hsin-Lung; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:52Z |
Energy-efficient flash-memory storage systems with an interrupt-emulation mechanism.
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CHIA-LIN YANG; Yang, Chia-Lin; Kuo, Tei-Wei; Wu, Chin-Hsien; Wu, Chin-Hsien;Kuo, Tei-Wei;Yang, Chia-Lin |
| 臺大學術典藏 |
2020-05-04T07:27:51Z |
Branch Behavior Characterization for Multimedia Applications.
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Yang, Chia-Lin; Wang, Shun-Ying; Chen, Yi-Jung; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:51Z |
Placement of digital microfluidic biochips using the t-tree formulation.
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Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:51Z |
Hierarchical value cache encoding for off-chip data bus.
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Lin, Chung-Hsiang; Yang, Chia-Lin; King, Ku-Jei; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:51Z |
An energy-efficient virtual memory system with flash memory as the secondary storage.
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Tseng, Hung-Wei;Li, Han-Lin;Yang, Chia-Lin; Tseng, Hung-Wei; Li, Han-Lin; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:51Z |
A Space-Efficient Caching Mechanism for Flash-Memory Address Translation.
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Wu, Chin-Hsien; Kuo, Tei-Wei; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:50Z |
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs.
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Li, Chi-Feng; Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:50Z |
Efficient obstacle-avoiding rectilinear steiner tree construction.
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CHIA-LIN YANG; Yang, Chia-Lin; Chang, Yao-Wen; Li, Chi-Feng; Chen, Szu-Yu; Lin, Chung-Wei |
| 臺大學術典藏 |
2020-05-04T07:27:49Z |
PPT: joint performance/power/thermal management of DRAM memory for multi-core systems.
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Lin, Chung-Hsiang;Yang, Chia-Lin;King, Ku-Jei; Lin, Chung-Hsiang; Yang, Chia-Lin; King, Ku-Jei; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:49Z |
A progressive-ILP based routing algorithm for cross-referencing biochips.
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Yuh, Ping-Hung;Sapatnekar, Sachin S.;Yang, Chia-Lin;Chang, Yao-Wen; Yuh, Ping-Hung; Sapatnekar, Sachin S.; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:49Z |
Cache leakage control mechanism for hard real-time systems.
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Chi, Jaw-Wei;Yang, Chia-Lin;Chen, Yi-Jung;Chen, Jian-Jia; Chi, Jaw-Wei; Yang, Chia-Lin; Chen, Yi-Jung; Chen, Jian-Jia; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:49Z |
BioRoute: a network-flow based routing algorithm for digital microfluidic biochips.
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Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:49Z |
3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design.
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Chien, Shao-Yi; Shih, Chi-Sheng; Ku, Mong-Kai; Yang, Chia-Lin; Chang, Yao-Wen; Kuo, Tei-Wei; Chen, Liang-Gee; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:48Z |
Hierarchical memory scheduling for multimedia MPSoCs.
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Lin, Ye-Jyun;Yang, Chia-Lin;Lin, Tay-Jyi;Huang, Jiao-Wei;Chang, Naehyuck; Lin, Ye-Jyun; Yang, Chia-Lin; Lin, Tay-Jyi; Huang, Jiao-Wei; Chang, Naehyuck; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:48Z |
Parallelization and characterization of GARCH option pricing on GPUs.
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Liu, Ren-Shuo;Tsai, Yun-Cheng;Yang, Chia-Lin; Liu, Ren-Shuo; Tsai, Yun-Cheng; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:48Z |
Memory Latency Reduction via Thread Throttling.
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Cheng, Hsiang-Yun;Lin, Chung-Hsiang;Li, Jian;Yang, Chia-Lin; Cheng, Hsiang-Yun; Lin, Chung-Hsiang; Li, Jian; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:48Z |
Thermal modeling for 3D-ICs with integrated microchannel cooling.
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Lu, Yi-Chang; Yang, Chia-Lin; Mizunuma, Hitoshi;Yang, Chia-Lin;Lu, Yi-Chang; Mizunuma, Hitoshi; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:47Z |
Optimizing NAND flash-based SSDs via retention relaxation.
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Liu, Ren-Shuo; Yang, Chia-Lin; Wu, Wei; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:47Z |
Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs.
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Chen, Yi-Jung; Yang, Chia-Lin; Chen, Jian-Jia; CHIA-LIN YANG |
Showing items 16-40 of 190 (8 Page(s) Totally)
1 2 3 4 5 6 7 8 > >>
View [10|25|50] records per page
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