|
"yang chia lin"的相關文件
顯示項目 36-60 / 190 (共8頁)
<< < 1 2 3 4 5 6 7 8 > >>
每頁顯示[10|25|50]項目
| 臺大學術典藏 |
2020-05-04T07:27:48Z |
Parallelization and characterization of GARCH option pricing on GPUs.
|
Liu, Ren-Shuo;Tsai, Yun-Cheng;Yang, Chia-Lin; Liu, Ren-Shuo; Tsai, Yun-Cheng; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:48Z |
Memory Latency Reduction via Thread Throttling.
|
Cheng, Hsiang-Yun;Lin, Chung-Hsiang;Li, Jian;Yang, Chia-Lin; Cheng, Hsiang-Yun; Lin, Chung-Hsiang; Li, Jian; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:48Z |
Thermal modeling for 3D-ICs with integrated microchannel cooling.
|
Lu, Yi-Chang; Yang, Chia-Lin; Mizunuma, Hitoshi;Yang, Chia-Lin;Lu, Yi-Chang; Mizunuma, Hitoshi; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:47Z |
Optimizing NAND flash-based SSDs via retention relaxation.
|
Liu, Ren-Shuo; Yang, Chia-Lin; Wu, Wei; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:47Z |
Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs.
|
Chen, Yi-Jung; Yang, Chia-Lin; Chen, Jian-Jia; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:47Z |
A SAT-based routing algorithm for cross-referencing biochips.
|
Yuh, Ping-Hung;Lin, Cliff Chiung-Yu;Huang, Tsung-Wei;Ho, Tsung-Yi;Yang, Chia-Lin;Chang, Yao-Wen; Yuh, Ping-Hung; Lin, Cliff Chiung-Yu; Huang, Tsung-Wei; Ho, Tsung-Yi; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:47Z |
SECRET: Selective error correction for refresh energy reduction in DRAMs.
|
Chen, Yi-Jung; Yang, Chia-Lin; Wang, Cheng-Yuan Michael; CHIA-LIN YANG; Shen, De-Yu; Lin, Chung-Hsiang; Lin, Chung-Hsiang;Shen, De-Yu;Chen, Yi-Jung;Yang, Chia-Lin;Wang, Cheng-Yuan Michael |
| 臺大學術典藏 |
2020-05-04T07:27:46Z |
Full system simulation framework for integrated CPU/GPU architecture.
|
Wang, Po-Han;Liu, Gen-Hong;Yeh, Jen-Chieh;Chen, Tse-Min;Huang, Hsu-Yao;Yang, Chia-Lin;Liu, Shih-Lien;Greensky, James; Wang, Po-Han; Liu, Gen-Hong; Yeh, Jen-Chieh; Chen, Tse-Min; Huang, Hsu-Yao; Yang, Chia-Lin; Liu, Shih-Lien; Greensky, James; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:46Z |
DuraCache: a durable SSD cache using MLC NAND flash.
|
Liu, Ren-Shuo;Yang, Chia-Lin;Li, Cheng-Hsuan;Chen, Geng-You; Liu, Ren-Shuo; Yang, Chia-Lin; Li, Cheng-Hsuan; Chen, Geng-You; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:46Z |
Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs.
|
Lin, Ping-Sheng;Chen, Yi-Jung;Yang, Chia-Lin;Lu, Yi-Chang; Lin, Ping-Sheng; Chen, Yi-Jung; Yang, Chia-Lin; Lu, Yi-Chang; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:46Z |
Thermal coupling aware task migration using neighboring core search for many-core systems.
|
Lu, Yi-Chang; Yang, Chia-Lin; CHIA-LIN YANG; Mizunuma, Hitoshi; Mizunuma, Hitoshi;Lu, Yi-Chang;Yang, Chia-Lin |
| 臺大學術典藏 |
2020-05-04T07:27:46Z |
Memory access aware power gating for MPSoCs.
|
Lin, Ye-Jyun; Lin, Ye-Jyun;Yang, Chia-Lin;Huang, Jiao-Wei;Chang, Naehyuck; Yang, Chia-Lin; Huang, Jiao-Wei; Chang, Naehyuck; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:45Z |
Improving DRAM latency with dynamic asymmetric subarray.
|
Lu, Shih-Lien;Lin, Ying-Chen;Yang, Chia-Lin; Lu, Shih-Lien; Lin, Ying-Chen; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:45Z |
A buffer cache architecture for smartphones with hybrid DRAM/PCM memory.
|
CHIA-LIN YANG; Wang, Cheng-Yuan Michael; Li, Hsiang-Pang; Yang, Chia-Lin; Lin, Ye-Jyun; Lin, Ye-Jyun;Yang, Chia-Lin;Li, Hsiang-Pang;Wang, Cheng-Yuan Michael |
| 臺大學術典藏 |
2020-05-04T07:27:45Z |
NVM duet: unified working memory and persistent store architecture.
|
Liu, Ren-Shuo;Shen, De-Yu;Yang, Chia-Lin;Yu, Shun-Chih;Wang, Cheng-Yuan Michael; Liu, Ren-Shuo; Shen, De-Yu; Yang, Chia-Lin; Yu, Shun-Chih; Wang, Cheng-Yuan Michael; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:45Z |
EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs.
|
Liu, Ren-Shuo;Chuang, Meng-Yen;Yang, Chia-Lin;Li, Cheng-Hsuan;Ho, Kin-Chu;Li, Hsiang-Pang; Liu, Ren-Shuo; Chuang, Meng-Yen; Yang, Chia-Lin; Li, Cheng-Hsuan; Ho, Kin-Chu; Li, Hsiang-Pang; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:44Z |
Message from the general co-chairs.
|
Garrett, David; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:44Z |
Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator.
|
Wang, Li;Tsai, Ren-Wei;Wang, Shao-Chung;Chen, Kun-Chih;Wang, Po-Han;Cheng, Hsiang-Yun;Lee, Yi-Chung;Shu, Sheng-Jie;Yang, Chun-Chieh;Hsu, Min-Yih;Kan, Li-Chen;Lee, Chao-Lin;Yu, Tzu-Chieh;Peng, Rih-Ding;Yang, Chia-Lin;Hwang, Yuan-Shin;Lee, Jenq Kuen;Tsao, Shiao-Li;Ouhyoung, Ming; Wang, Li; Tsai, Ren-Wei; Wang, Shao-Chung; Chen, Kun-Chih; Wang, Po-Han; Cheng, Hsiang-Yun; Lee, Yi-Chung; Shu, Sheng-Jie; Yang, Chun-Chieh; Hsu, Min-Yih; Kan, Li-Chen; Lee, Chao-Lin; Yu, Tzu-Chieh; Peng, Rih-Ding; Yang, Chia-Lin; Hwang, Yuan-Shin; Lee, Jenq Kuen; Tsao, Shiao-Li; Ouhyoung, Ming; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:44Z |
Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture.
|
Wang, Po-Han;Li, Cheng-Hsuan;Yang, Chia-Lin; Wang, Po-Han; Li, Cheng-Hsuan; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:44Z |
MCSSim: A memory channel storage simulator.
|
Chen, Renhai;Shao, Zili;Yang, Chia-Lin;Li, Tao; Chen, Renhai; Shao, Zili; Yang, Chia-Lin; Li, Tao; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:43Z |
Fair Down to the Device: A GC-Aware Fair Scheduler for SSD.
|
Ji, Cheng;Wang, Lun;Li, Qiao;Gao, Congming;Shi, Liang;Yang, Chia-Lin;Xue, Chun Jason; Ji, Cheng; Wang, Lun; Li, Qiao; Gao, Congming; Shi, Liang; Yang, Chia-Lin; Xue, Chun Jason; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:43Z |
Enabling fast preemption via Dual-Kernel support on GPUs.
|
CHIA-LIN YANG; Yang, Chia-Lin; Wang, Po-Han; Fu, Hsueh-Chun; Chen, Kun-Chih; Shieh, Li-Wei; Shieh, Li-Wei;Chen, Kun-Chih;Fu, Hsueh-Chun;Wang, Po-Han;Yang, Chia-Lin |
| 臺大學術典藏 |
2020-05-04T07:27:43Z |
Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating Approach.
|
Lai, Chun-Hao; Zhao, Jishen; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:43Z |
Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures.
|
Fu, Hsueh-Chun; Wang, Po-Han; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:42Z |
Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling
|
Chen, Li-Jhan;Cheng, Hsiang-Yun;Wang, Po-Han;Yang, Chia-Lin; Chen, Li-Jhan; Cheng, Hsiang-Yun; Wang, Po-Han; Yang, Chia-Lin; CHIA-LIN YANG |
顯示項目 36-60 / 190 (共8頁)
<< < 1 2 3 4 5 6 7 8 > >>
每頁顯示[10|25|50]項目
|
