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"yang chia lin"的相關文件
顯示項目 51-100 / 190 (共4頁)
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| 臺大學術典藏 |
2020-05-04T07:27:45Z |
EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs.
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Liu, Ren-Shuo;Chuang, Meng-Yen;Yang, Chia-Lin;Li, Cheng-Hsuan;Ho, Kin-Chu;Li, Hsiang-Pang; Liu, Ren-Shuo; Chuang, Meng-Yen; Yang, Chia-Lin; Li, Cheng-Hsuan; Ho, Kin-Chu; Li, Hsiang-Pang; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:44Z |
Message from the general co-chairs.
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Garrett, David; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:44Z |
Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator.
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Wang, Li;Tsai, Ren-Wei;Wang, Shao-Chung;Chen, Kun-Chih;Wang, Po-Han;Cheng, Hsiang-Yun;Lee, Yi-Chung;Shu, Sheng-Jie;Yang, Chun-Chieh;Hsu, Min-Yih;Kan, Li-Chen;Lee, Chao-Lin;Yu, Tzu-Chieh;Peng, Rih-Ding;Yang, Chia-Lin;Hwang, Yuan-Shin;Lee, Jenq Kuen;Tsao, Shiao-Li;Ouhyoung, Ming; Wang, Li; Tsai, Ren-Wei; Wang, Shao-Chung; Chen, Kun-Chih; Wang, Po-Han; Cheng, Hsiang-Yun; Lee, Yi-Chung; Shu, Sheng-Jie; Yang, Chun-Chieh; Hsu, Min-Yih; Kan, Li-Chen; Lee, Chao-Lin; Yu, Tzu-Chieh; Peng, Rih-Ding; Yang, Chia-Lin; Hwang, Yuan-Shin; Lee, Jenq Kuen; Tsao, Shiao-Li; Ouhyoung, Ming; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:44Z |
Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture.
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Wang, Po-Han;Li, Cheng-Hsuan;Yang, Chia-Lin; Wang, Po-Han; Li, Cheng-Hsuan; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:44Z |
MCSSim: A memory channel storage simulator.
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Chen, Renhai;Shao, Zili;Yang, Chia-Lin;Li, Tao; Chen, Renhai; Shao, Zili; Yang, Chia-Lin; Li, Tao; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:43Z |
Fair Down to the Device: A GC-Aware Fair Scheduler for SSD.
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Ji, Cheng;Wang, Lun;Li, Qiao;Gao, Congming;Shi, Liang;Yang, Chia-Lin;Xue, Chun Jason; Ji, Cheng; Wang, Lun; Li, Qiao; Gao, Congming; Shi, Liang; Yang, Chia-Lin; Xue, Chun Jason; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:43Z |
Enabling fast preemption via Dual-Kernel support on GPUs.
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CHIA-LIN YANG; Yang, Chia-Lin; Wang, Po-Han; Fu, Hsueh-Chun; Chen, Kun-Chih; Shieh, Li-Wei; Shieh, Li-Wei;Chen, Kun-Chih;Fu, Hsueh-Chun;Wang, Po-Han;Yang, Chia-Lin |
| 臺大學術典藏 |
2020-05-04T07:27:43Z |
Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating Approach.
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Lai, Chun-Hao; Zhao, Jishen; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:43Z |
Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures.
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Fu, Hsueh-Chun; Wang, Po-Han; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:42Z |
Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling
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Chen, Li-Jhan;Cheng, Hsiang-Yun;Wang, Po-Han;Yang, Chia-Lin; Chen, Li-Jhan; Cheng, Hsiang-Yun; Wang, Po-Han; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:42Z |
NVM Duet: Unified Working Memory and Persistent Store Architecture
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Liu, Ren-Shuo;Shen, De-Yu;Yang, Chia-Lin;Yu, Shun-Chih;Wang, Cheng-Yuan Michael; Liu, Ren-Shuo; Shen, De-Yu; Yang, Chia-Lin; Yu, Shun-Chih; Wang, Cheng-Yuan Michael; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:42Z |
Branch behavior characterization for multimedia applications
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Yang, Chia-Lin; Wang, Shun-Ying; Chen, Yi-Jung; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:42Z |
Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks.
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Yang, Tzu-Hsien;Cheng, Hsiang-Yun;Yang, Chia-Lin;Tseng, I-Ching;Hu, Han-Wen;Chang, Hung-Sheng;Li, Hsiang-Pang; CHIA-LIN YANG; Li, Hsiang-Pang; Chang, Hung-Sheng; Yang, Tzu-Hsien; Cheng, Hsiang-Yun; Yang, Chia-Lin; Tseng, I-Ching; Hu, Han-Wen |
| 臺大學術典藏 |
2020-05-04T07:27:42Z |
Opportunities of Synergistically Adjusting Voltage-Frequency Levels of Cores and DRAMs in CMPs with 3D-Stacked DRAMs for Efficient Thermal Control
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Chen, Yi-Jung;Yang, Chia-Lin;Lin, Pin-Sheng;Lu, Yi-Chang; Chen, Yi-Jung; Yang, Chia-Lin; Lin, Pin-Sheng; Lu, Yi-Chang; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:41Z |
The impact of 2016 guideline on clinical practice for the management of hospital-acquired and ventilator-associated pneumonia in Taiwan
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Lin, Chi-Ying; CHIA-LIN YANG; Chen, Yen-Fu; Yang, Chia-Lin |
| 臺大學術典藏 |
2020-05-04T07:27:06Z |
Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations.
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AI-CHUN PANG; Kuo, Tei-Wei; Pang, Ai-Chun; Yang, Chia-Lin; Chuang, Kai-Hsiang; Hsu, Heng-Ruey; Chen, Jian-Jia |
| 臺大學術典藏 |
2018-09-10T07:37:14Z |
Thermal modeling for 3D-ICs with integrated microchannel cooling
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Mizunuma, Hitoshi;Yang, Chia-Lin;Lu, Yi-Chang; Mizunuma, Hitoshi; Yang, Chia-Lin; Lu, Yi-Chang; YI-CHANG LU |
| 臺大學術典藏 |
2018-09-10T07:33:29Z |
Content-aware energy prediction for video streaming in mobile devices
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Li, Han-Lin; Yang, Chia-Lin; CHIA-LIN YANG; Shun, Chia-Tung; Li, Yi-Chan; Li, Hisu-Hsien; Li, Yi-Chan;Li, Hisu-Hsien;Li, Han-Lin;Yang, Chia-Lin |
| 臺大學術典藏 |
2018-09-10T07:33:29Z |
A predictive shutdown technique for GPU shader processors
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Wang, Po-Han;Chen, Yen-Ming;Yang, Chia-Lin;Cheng, Yu-Jung; Wang, Po-Han; Chen, Yen-Ming; Yang, Chia-Lin; Cheng, Yu-Jung; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T07:30:37Z |
A multi-core architecture based parallel framework for h.264/avc deblocking filters
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Wang, Sung-Wen;Yang, Shu-Sian;Chen, Hong-Ming;Yang, Chia-Lin;Wu, Ja-Ling; Wang, Sung-Wen; Yang, Shu-Sian; Chen, Hong-Ming; Yang, Chia-Lin; Wu, Ja-Ling; JA-LING WU; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T07:03:50Z |
A progressive-ILP based routing algorithm for cross-referencing biochips
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Yuh, Ping-Hung; Sapatnekar, S.; Yang, Chia-Lin; Chang, Yao-Wen; YAO-WEN CHANG; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T07:03:49Z |
BioRoute: A network-flow-based routing algorithm for the synthesis of digital microfluidic biochips
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Yuh, Ping-Hung;Yang, Chia-Lin;Chang, Yao-Wen; Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; YAO-WEN CHANG; Yang, Chia-Lin |
| 臺大學術典藏 |
2018-09-10T07:00:36Z |
Energy-aware flash memory management in virtual memory system
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Li, Han-Lin;Yang, Chia-Lin;Tseng, Hung-Wei; Li, Han-Lin; Yang, Chia-Lin; Tseng, Hung-Wei; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T07:00:36Z |
Exploiting instruction level parallelism in geometry processing for three dimensional graphics applications
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Yang, Chia-Lin; Sano, Barton; Lebeck, Alvin R.; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T07:00:35Z |
Tunablevp: a tunable virtual platform for easy soc design space exploration
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Lin, Ye-Jyun; Chen, Yi-Jung; Huang, Chin-Chie; Lin, Tzu-Ching; Chi, Jaw-Wei; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T06:31:00Z |
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation
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Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; Yang, Chia-Lin |
| 臺大學術典藏 |
2018-09-10T06:30:59Z |
Temporal floorplanning using the three-dimensional transitive closure subGraph
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Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; Yang, Chia-Lin |
| 臺大學術典藏 |
2018-09-10T06:27:37Z |
An architectural co-synthesis algorithm for energy-aware network-on-chip design
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Hung, Wei-Hsuan;Chen, Yi-Jung;Yang, Chia-Lin;Chang, Yen-Sheng;Su, Alan P.; Hung, Wei-Hsuan; Chen, Yi-Jung; Yang, Chia-Lin; Chang, Yen-Sheng; Su, Alan P.; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T05:20:41Z |
Reconfigurable platform for content science research
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Shih, C.-S.; Yang, C.-L.; Ku, M.-K.; Kuo, T.-W.; Chien, S.-Y.; Chang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN; Shih, Chi-Sheng; Yang, Chia-Lin; TEI-WEI KUO; YAO-WEN CHANG; SHAO-YI CHIEN |
| 臺大學術典藏 |
2018-09-10T05:18:22Z |
Software-controlled cache architecture for energy efficiency
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Yang, Chia-Lin;Tseng, Hung-Wei;Ho, Chia-Chiang;Wu, Ja-Ling; Yang, Chia-Lin; Tseng, Hung-Wei; Ho, Chia-Chiang; Wu, Ja-Ling; JA-LING WU; Yang, Chia-Lin |
| 臺大學術典藏 |
2018-09-10T04:31:08Z |
Smart cache: An energy-efficient D-cache for a software MPEG-2 video decoder
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Yang, Chia-Lin;Tseng, Hung-Wei;Ho, Chia-Chiang; Yang, Chia-Lin; Tseng, Hung-Wei; Ho, Chia-Chiang; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T03:28:17Z |
Push vs. pull: Data movement for linked data structures
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Yang, Chia-Lin; Lebeck, Alvin R.; CHIA-LIN YANG |
| 國立交通大學 |
2018-08-21T05:57:06Z |
Analyzing OpenCL 2.0 Workloads Using a Heterogeneous CPU-GPU Simulator
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Wang, Li; Tsai, Ren-Wei; Wang, Shao-Chung; Chen, Kun-Chih; Wang, Po-Han; Cheng, Hsiang-Yun; Lee, Yi-Chung; Shu, Sheng-Jie; Yang, Chun-Chieh; Hsu, Min-Yih; Kan, Li-Chen; Lee, Chao-Lin; Yu, Tzu-Chieh; Peng, Rih-Ding; Yang, Chia-Lin; Hwang, Yuan-Shin; Lee, Jenq-Kuen; Tsao, Shiao-Li; Ouhyoung, Ming |
| 臺大學術典藏 |
2018-07-05T01:59:29Z |
A Space-Efficient Caching Mechanism for Flash-Memory Address Translation
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Yang, Chia-Lin; Kuo, Tei-Wei; Wu, Chin-Hsien; Wu, Chin-Hsien; Kuo, Tei-Wei; Yang, Chia-Lin |
| 臺大學術典藏 |
2018-07-05T01:55:22Z |
Tolerating Memory Latency Through Push Prefetching for Pointer-Intensive Applications
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Lee, Chien-Hao; Tseng, Hung-Wei; Lebeck, Alvin R.; Yang, Chia-Lin; Lebeck, Alvin R.; Tseng, Hung-Wei; Lee, Chien-Hao; Yang, Chia-Lin |
| 臺大學術典藏 |
2018-07-05T01:53:24Z |
Hierarchical Value Cache Encoding for Off-Chip Data Bus
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King, Ku-Jei; Yang, Chia-Lin; Lin, Chung-Hsiang; Lin, Chung-Hsiang; Yang, Chia-Lin; King, Ku-Jei |
| 臺大學術典藏 |
2018 |
DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning.
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Li, Hsiang-Pang; Chang, Meng-Fan; CHIA-LIN YANG; Chang, Hung-Sheng; Lin, Meng-Yao;Cheng, Hsiang-Yun;Lin, Wei-Ting;Yang, Tzu-Hsien;Tseng, I-Ching;Yang, Chia-Lin;Hu, Han-Wen;Chang, Hung-Sheng;Li, Hsiang-Pang;Chang, Meng-Fan; Lin, Meng-Yao; Cheng, Hsiang-Yun; Lin, Wei-Ting; Yang, Tzu-Hsien; Tseng, I-Ching; Yang, Chia-Lin; Hu, Han-Wen |
| 國立交通大學 |
2017-04-21T06:56:47Z |
Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality
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Liu, Ren-Shuo; Chuang, Meng-Yen; Yang, Chia-Lin; Li, Cheng-Hsuan; Ho, Kin-Chu; Li, Hsiang-Pang |
| 臺大學術典藏 |
2017 |
Recap of the 2017 International Symposium on Low Power Electronics and Design (ISLPED)
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CHIA-LIN YANG; Garrett, David; Yang, Chia-Lin |
| 國立成功大學 |
2016-10 |
Effect of annealing temperature on the optoelectronic characteristic of Al and Ga co-doping ZnO thin films
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Tsai, Tang-Yi; Chen, Tao-Hsing; Tu, Sheng-Lung; Su, Yen-Hsun; Shen, Yun-Hwei; Yang, Chia-Lin |
| 國立高雄應用科技大學 |
2016 |
不同製程參數對Mg:GZO透明導電膜之光電特性的影響
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楊佳霖; Yang, Chia-Lin |
| 國立高雄應用科技大學 |
2016 |
居民的的社區意識、活動認同感與活動涉入之相關研究－以台東縣熱氣球嘉年華為例
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楊佳陵; YANG, CHIA- LIN |
| 臺大學術典藏 |
2015 |
Fine-grained write scheduling for PCM performance improvement under write power budget.
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CHIA-LIN YANG; Li, Hsiang-Pang; Lai, Chun-Hao;Yu, Shun-Chih;Yang, Chia-Lin;Li, Hsiang-Pang; Lai, Chun-Hao; Yu, Shun-Chih; Yang, Chia-Lin |
| 臺大學術典藏 |
2015 |
Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs.
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Lin, Ping-Sheng; Lu, Yi-Chang; CHIA-LIN YANG; Chen, Yi-Jung;Yang, Chia-Lin;Lin, Ping-Sheng;Lu, Yi-Chang; Chen, Yi-Jung; Yang, Chia-Lin |
| 臺大學術典藏 |
2012 |
Age-based PCM wear leveling with nearly zero search cost.
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CHIA-LIN YANG; Wang, Cheng-Yuan Michael; Chen, Chi-Hao; Hsiu, Pi-Cheng; Kuo, Tei-Wei; Yang, Chia-Lin |
| 臺大學術典藏 |
2012 |
A cycle-level SIMT-GPU simulation framework.
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Wang, Po-Han; Lo, Chien-Wei; Yang, Chia-Lin; Cheng, Yu-Jung; CHIA-LIN YANG |
| 臺大學術典藏 |
2012 |
Age-based PCM wear leveling with nearly zero search cost.
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Chen, Chi-Hao; Hsiu, Pi-Cheng; Kuo, Tei-Wei; Yang, Chia-Lin; Wang, Cheng-Yuan Michael; TEI-WEI KUO |
| 國立成功大學 |
2011-08-05 |
探討Twist Snail Slug和E-cadherin於癌化過程及葡萄糖代謝在子宮頸癌扮演的角色
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楊佳霖; Yang, Chia-Lin |
| 國立成功大學 |
2010-06-09 |
車內視線高低影響乘坐者情緒變化之研究
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楊佳霖; Yang, Chia-Lin |
| 臺大學術典藏 |
2010 |
PM-COSYN: PE and memory co-synthesis for MPSoCs.
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Yang, Chia-Lin; Chen, Yi-Jung; Chen, Yi-Jung;Yang, Chia-Lin;Wang, Po-Han; Wang, Po-Han; CHIA-LIN YANG |
顯示項目 51-100 / 190 (共4頁)
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