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教育部委託研究計畫      計畫執行:國立臺灣大學圖書館
 
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顯示項目 56-80 / 190 (共8頁)
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機構 日期 題名 作者
臺大學術典藏 2020-05-04T07:27:43Z Fair Down to the Device: A GC-Aware Fair Scheduler for SSD. Ji, Cheng;Wang, Lun;Li, Qiao;Gao, Congming;Shi, Liang;Yang, Chia-Lin;Xue, Chun Jason; Ji, Cheng; Wang, Lun; Li, Qiao; Gao, Congming; Shi, Liang; Yang, Chia-Lin; Xue, Chun Jason; CHIA-LIN YANG
臺大學術典藏 2020-05-04T07:27:43Z Enabling fast preemption via Dual-Kernel support on GPUs. CHIA-LIN YANG; Yang, Chia-Lin; Wang, Po-Han; Fu, Hsueh-Chun; Chen, Kun-Chih; Shieh, Li-Wei; Shieh, Li-Wei;Chen, Kun-Chih;Fu, Hsueh-Chun;Wang, Po-Han;Yang, Chia-Lin
臺大學術典藏 2020-05-04T07:27:43Z Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating Approach. Lai, Chun-Hao; Zhao, Jishen; Yang, Chia-Lin; CHIA-LIN YANG
臺大學術典藏 2020-05-04T07:27:43Z Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures. Fu, Hsueh-Chun; Wang, Po-Han; Yang, Chia-Lin; CHIA-LIN YANG
臺大學術典藏 2020-05-04T07:27:42Z Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling Chen, Li-Jhan;Cheng, Hsiang-Yun;Wang, Po-Han;Yang, Chia-Lin; Chen, Li-Jhan; Cheng, Hsiang-Yun; Wang, Po-Han; Yang, Chia-Lin; CHIA-LIN YANG
臺大學術典藏 2020-05-04T07:27:42Z NVM Duet: Unified Working Memory and Persistent Store Architecture Liu, Ren-Shuo;Shen, De-Yu;Yang, Chia-Lin;Yu, Shun-Chih;Wang, Cheng-Yuan Michael; Liu, Ren-Shuo; Shen, De-Yu; Yang, Chia-Lin; Yu, Shun-Chih; Wang, Cheng-Yuan Michael; CHIA-LIN YANG
臺大學術典藏 2020-05-04T07:27:42Z Branch behavior characterization for multimedia applications Yang, Chia-Lin; Wang, Shun-Ying; Chen, Yi-Jung; CHIA-LIN YANG
臺大學術典藏 2020-05-04T07:27:42Z Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks. Yang, Tzu-Hsien;Cheng, Hsiang-Yun;Yang, Chia-Lin;Tseng, I-Ching;Hu, Han-Wen;Chang, Hung-Sheng;Li, Hsiang-Pang; CHIA-LIN YANG; Li, Hsiang-Pang; Chang, Hung-Sheng; Yang, Tzu-Hsien; Cheng, Hsiang-Yun; Yang, Chia-Lin; Tseng, I-Ching; Hu, Han-Wen
臺大學術典藏 2020-05-04T07:27:42Z Opportunities of Synergistically Adjusting Voltage-Frequency Levels of Cores and DRAMs in CMPs with 3D-Stacked DRAMs for Efficient Thermal Control Chen, Yi-Jung;Yang, Chia-Lin;Lin, Pin-Sheng;Lu, Yi-Chang; Chen, Yi-Jung; Yang, Chia-Lin; Lin, Pin-Sheng; Lu, Yi-Chang; CHIA-LIN YANG
臺大學術典藏 2020-05-04T07:27:41Z The impact of 2016 guideline on clinical practice for the management of hospital-acquired and ventilator-associated pneumonia in Taiwan Lin, Chi-Ying; CHIA-LIN YANG; Chen, Yen-Fu; Yang, Chia-Lin
臺大學術典藏 2020-05-04T07:27:06Z Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations. AI-CHUN PANG; Kuo, Tei-Wei; Pang, Ai-Chun; Yang, Chia-Lin; Chuang, Kai-Hsiang; Hsu, Heng-Ruey; Chen, Jian-Jia
臺大學術典藏 2018-09-10T07:37:14Z Thermal modeling for 3D-ICs with integrated microchannel cooling Mizunuma, Hitoshi;Yang, Chia-Lin;Lu, Yi-Chang; Mizunuma, Hitoshi; Yang, Chia-Lin; Lu, Yi-Chang; YI-CHANG LU
臺大學術典藏 2018-09-10T07:33:29Z Content-aware energy prediction for video streaming in mobile devices Li, Han-Lin; Yang, Chia-Lin; CHIA-LIN YANG; Shun, Chia-Tung; Li, Yi-Chan; Li, Hisu-Hsien; Li, Yi-Chan;Li, Hisu-Hsien;Li, Han-Lin;Yang, Chia-Lin
臺大學術典藏 2018-09-10T07:33:29Z A predictive shutdown technique for GPU shader processors Wang, Po-Han;Chen, Yen-Ming;Yang, Chia-Lin;Cheng, Yu-Jung; Wang, Po-Han; Chen, Yen-Ming; Yang, Chia-Lin; Cheng, Yu-Jung; CHIA-LIN YANG
臺大學術典藏 2018-09-10T07:30:37Z A multi-core architecture based parallel framework for h.264/avc deblocking filters Wang, Sung-Wen;Yang, Shu-Sian;Chen, Hong-Ming;Yang, Chia-Lin;Wu, Ja-Ling; Wang, Sung-Wen; Yang, Shu-Sian; Chen, Hong-Ming; Yang, Chia-Lin; Wu, Ja-Ling; JA-LING WU; CHIA-LIN YANG
臺大學術典藏 2018-09-10T07:03:50Z A progressive-ILP based routing algorithm for cross-referencing biochips Yuh, Ping-Hung; Sapatnekar, S.; Yang, Chia-Lin; Chang, Yao-Wen; YAO-WEN CHANG; CHIA-LIN YANG
臺大學術典藏 2018-09-10T07:03:49Z BioRoute: A network-flow-based routing algorithm for the synthesis of digital microfluidic biochips Yuh, Ping-Hung;Yang, Chia-Lin;Chang, Yao-Wen; Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; YAO-WEN CHANG; Yang, Chia-Lin
臺大學術典藏 2018-09-10T07:00:36Z Energy-aware flash memory management in virtual memory system Li, Han-Lin;Yang, Chia-Lin;Tseng, Hung-Wei; Li, Han-Lin; Yang, Chia-Lin; Tseng, Hung-Wei; CHIA-LIN YANG
臺大學術典藏 2018-09-10T07:00:36Z Exploiting instruction level parallelism in geometry processing for three dimensional graphics applications Yang, Chia-Lin; Sano, Barton; Lebeck, Alvin R.; CHIA-LIN YANG
臺大學術典藏 2018-09-10T07:00:35Z Tunablevp: a tunable virtual platform for easy soc design space exploration Lin, Ye-Jyun; Chen, Yi-Jung; Huang, Chin-Chie; Lin, Tzu-Ching; Chi, Jaw-Wei; Yang, Chia-Lin; CHIA-LIN YANG
臺大學術典藏 2018-09-10T06:31:00Z Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; Yang, Chia-Lin
臺大學術典藏 2018-09-10T06:30:59Z Temporal floorplanning using the three-dimensional transitive closure subGraph Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; Yang, Chia-Lin
臺大學術典藏 2018-09-10T06:27:37Z An architectural co-synthesis algorithm for energy-aware network-on-chip design Hung, Wei-Hsuan;Chen, Yi-Jung;Yang, Chia-Lin;Chang, Yen-Sheng;Su, Alan P.; Hung, Wei-Hsuan; Chen, Yi-Jung; Yang, Chia-Lin; Chang, Yen-Sheng; Su, Alan P.; CHIA-LIN YANG
臺大學術典藏 2018-09-10T05:20:41Z Reconfigurable platform for content science research Shih, C.-S.; Yang, C.-L.; Ku, M.-K.; Kuo, T.-W.; Chien, S.-Y.; Chang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN; Shih, Chi-Sheng; Yang, Chia-Lin; TEI-WEI KUO; YAO-WEN CHANG; SHAO-YI CHIEN
臺大學術典藏 2018-09-10T05:18:22Z Software-controlled cache architecture for energy efficiency Yang, Chia-Lin;Tseng, Hung-Wei;Ho, Chia-Chiang;Wu, Ja-Ling; Yang, Chia-Lin; Tseng, Hung-Wei; Ho, Chia-Chiang; Wu, Ja-Ling; JA-LING WU; Yang, Chia-Lin

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