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Showing items 1-50 of 190 (4 Page(s) Totally)
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| 臺大學術典藏 |
2020-05-04T08:07:13Z |
Profit-driven uniprocessor scheduling with energy and timing constraints.
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Chen, Jian-Jia;Kuo, Tei-Wei;Yang, Chia-Lin; Chen, Jian-Jia; Kuo, Tei-Wei; Yang, Chia-Lin; TEI-WEI KUO |
| 臺大學術典藏 |
2020-05-04T08:07:11Z |
Energy-efficient flash-memory storage systems with an interrupt-emulation mechanism.
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Wu, Chin-Hsien;Kuo, Tei-Wei;Yang, Chia-Lin; Wu, Chin-Hsien; Kuo, Tei-Wei; Yang, Chia-Lin; TEI-WEI KUO |
| 臺大學術典藏 |
2020-05-04T08:07:11Z |
Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations.
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Chen, Jian-Jia; Hsu, Heng-Ruey; Chuang, Kai-Hsiang; Yang, Chia-Lin; Pang, Ai-Chun; Kuo, Tei-Wei; TEI-WEI KUO |
| 臺大學術典藏 |
2020-05-04T08:07:10Z |
Reconfigurable Platform for Content Science Research.
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Shih, Chi-Sheng; Yang, Chia-Lin; Ku, Mong-Kai; Kuo, Tei-Wei; Chien, Shao-Yi; Chang, Yao-Wen; Chen, Liang-Gee; TEI-WEI KUO |
| 臺大學術典藏 |
2020-05-04T08:07:07Z |
A Space-Efficient Caching Mechanism for Flash-Memory Address Translation.
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Wu, Chin-Hsien; Kuo, Tei-Wei; Yang, Chia-Lin; TEI-WEI KUO |
| 臺大學術典藏 |
2020-05-04T08:07:03Z |
3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design.
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TEI-WEI KUO; Chen, Liang-Gee; Kuo, Tei-Wei; Chang, Yao-Wen; Yang, Chia-Lin; Ku, Mong-Kai; Shih, Chi-Sheng; Chien, Shao-Yi |
| 臺大學術典藏 |
2020-05-04T08:04:41Z |
Cache Leakage Management for Multi-programming Workloads.
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Chen, Chun-Yang; Yang, Chia-Lin; Hung, Shih-Hao; SHIH-HAO HUNG |
| 臺大學術典藏 |
2020-05-04T07:53:59Z |
Efficient obstacle-avoiding rectilinear steiner tree construction.
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Lin, Chung-Wei; Chen, Szu-Yu; Li, Chi-Feng; Chang, Yao-Wen; Yang, Chia-Lin; CHUNG-WEI LIN |
| 臺大學術典藏 |
2020-05-04T07:48:21Z |
System-Level Performance and Power Optimization for MPSoC: A Memory Access-Aware Approach
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Lin, Ye-Jyun;Yang, Chia-Lin;Huang, Jiao-We;Lin, Tay-Jyi;Hsueh, Chih-Wen;Chang, Naehyuck; Lin, Ye-Jyun; Yang, Chia-Lin; Huang, Jiao-We; Lin, Tay-Jyi; Hsueh, Chih-Wen; Chang, Naehyuck; CHIH-WEN HSUEH |
| 臺大學術典藏 |
2020-05-04T07:44:31Z |
3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design.
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CHI-SHENG SHIH; Chien, Shao-Yi; Shih, Chi-Sheng; Ku, Mong-Kai; Yang, Chia-Lin; Chang, Yao-Wen; Kuo, Tei-Wei; Chen, Liang-Gee |
| 臺大學術典藏 |
2020-05-04T07:27:55Z |
Annotated Memory References: A Mechanism for Informed Cache Management.
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Lebeck, Alvin R.; Raymond, David R.; Yang, Chia-Lin; Thottethodi, Mithuna; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:55Z |
Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications.
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Yang, Chia-Lin; Sano, Barton; Lebeck, Alvin R.; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:54Z |
Profit-driven uniprocessor scheduling with energy and timing constraints.
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Chen, Jian-Jia;Kuo, Tei-Wei;Yang, Chia-Lin; Chen, Jian-Jia; Kuo, Tei-Wei; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:54Z |
Using Intel Streaming SIMD Extensions for 3D Geometry Processing.
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CHIA-LIN YANG; Ma, Wan-Chun; Yang, Chia-Lin |
| 臺大學術典藏 |
2020-05-04T07:27:53Z |
Value-Conscious Cache: Simple Technique for Reducing Cache Access Power.
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Chang, Yen-Jen; Yang, Chia-Lin; Lai, Feipei; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:53Z |
Temporal floorplanning using the T-tree formulation.
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Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:53Z |
HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction.
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Yang, Chia-Lin; Lee, Chien-Hao; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:52Z |
Cache Leakage Management for Multi-programming Workloads.
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Chen, Chun-Yang; Yang, Chia-Lin; Hung, Shih-Hao; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:52Z |
Joint exploration of architectural and physical design spaces with thermal consideration.
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CHIA-LIN YANG; Chang, Yao-Wen; Yuh, Ping-Hung; Yang, Chia-Lin; Wu, Yen-Wei |
| 臺大學術典藏 |
2020-05-04T07:27:52Z |
Reconfigurable Platform for Content Science Research.
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Shih, Chi-Sheng; Yang, Chia-Lin; Ku, Mong-Kai; Kuo, Tei-Wei; Chien, Shao-Yi; Chang, Yao-Wen; Chen, Liang-Gee; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:52Z |
Temporal floorplanning using 3D-subTCG.
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Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; Chen, Hsin-Lung; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:52Z |
Energy-efficient flash-memory storage systems with an interrupt-emulation mechanism.
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CHIA-LIN YANG; Yang, Chia-Lin; Kuo, Tei-Wei; Wu, Chin-Hsien; Wu, Chin-Hsien;Kuo, Tei-Wei;Yang, Chia-Lin |
| 臺大學術典藏 |
2020-05-04T07:27:51Z |
Branch Behavior Characterization for Multimedia Applications.
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Yang, Chia-Lin; Wang, Shun-Ying; Chen, Yi-Jung; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:51Z |
Placement of digital microfluidic biochips using the t-tree formulation.
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Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:51Z |
Hierarchical value cache encoding for off-chip data bus.
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Lin, Chung-Hsiang; Yang, Chia-Lin; King, Ku-Jei; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:51Z |
An energy-efficient virtual memory system with flash memory as the secondary storage.
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Tseng, Hung-Wei;Li, Han-Lin;Yang, Chia-Lin; Tseng, Hung-Wei; Li, Han-Lin; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:51Z |
A Space-Efficient Caching Mechanism for Flash-Memory Address Translation.
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Wu, Chin-Hsien; Kuo, Tei-Wei; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:50Z |
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs.
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Li, Chi-Feng; Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:50Z |
Efficient obstacle-avoiding rectilinear steiner tree construction.
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CHIA-LIN YANG; Yang, Chia-Lin; Chang, Yao-Wen; Li, Chi-Feng; Chen, Szu-Yu; Lin, Chung-Wei |
| 臺大學術典藏 |
2020-05-04T07:27:49Z |
PPT: joint performance/power/thermal management of DRAM memory for multi-core systems.
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Lin, Chung-Hsiang;Yang, Chia-Lin;King, Ku-Jei; Lin, Chung-Hsiang; Yang, Chia-Lin; King, Ku-Jei; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:49Z |
A progressive-ILP based routing algorithm for cross-referencing biochips.
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Yuh, Ping-Hung;Sapatnekar, Sachin S.;Yang, Chia-Lin;Chang, Yao-Wen; Yuh, Ping-Hung; Sapatnekar, Sachin S.; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:49Z |
Cache leakage control mechanism for hard real-time systems.
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Chi, Jaw-Wei;Yang, Chia-Lin;Chen, Yi-Jung;Chen, Jian-Jia; Chi, Jaw-Wei; Yang, Chia-Lin; Chen, Yi-Jung; Chen, Jian-Jia; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:49Z |
BioRoute: a network-flow based routing algorithm for digital microfluidic biochips.
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Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:49Z |
3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design.
|
Chien, Shao-Yi; Shih, Chi-Sheng; Ku, Mong-Kai; Yang, Chia-Lin; Chang, Yao-Wen; Kuo, Tei-Wei; Chen, Liang-Gee; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:48Z |
Hierarchical memory scheduling for multimedia MPSoCs.
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Lin, Ye-Jyun;Yang, Chia-Lin;Lin, Tay-Jyi;Huang, Jiao-Wei;Chang, Naehyuck; Lin, Ye-Jyun; Yang, Chia-Lin; Lin, Tay-Jyi; Huang, Jiao-Wei; Chang, Naehyuck; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:48Z |
Parallelization and characterization of GARCH option pricing on GPUs.
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Liu, Ren-Shuo;Tsai, Yun-Cheng;Yang, Chia-Lin; Liu, Ren-Shuo; Tsai, Yun-Cheng; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:48Z |
Memory Latency Reduction via Thread Throttling.
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Cheng, Hsiang-Yun;Lin, Chung-Hsiang;Li, Jian;Yang, Chia-Lin; Cheng, Hsiang-Yun; Lin, Chung-Hsiang; Li, Jian; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:48Z |
Thermal modeling for 3D-ICs with integrated microchannel cooling.
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Lu, Yi-Chang; Yang, Chia-Lin; Mizunuma, Hitoshi;Yang, Chia-Lin;Lu, Yi-Chang; Mizunuma, Hitoshi; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:47Z |
Optimizing NAND flash-based SSDs via retention relaxation.
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Liu, Ren-Shuo; Yang, Chia-Lin; Wu, Wei; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:47Z |
Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs.
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Chen, Yi-Jung; Yang, Chia-Lin; Chen, Jian-Jia; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:47Z |
A SAT-based routing algorithm for cross-referencing biochips.
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Yuh, Ping-Hung;Lin, Cliff Chiung-Yu;Huang, Tsung-Wei;Ho, Tsung-Yi;Yang, Chia-Lin;Chang, Yao-Wen; Yuh, Ping-Hung; Lin, Cliff Chiung-Yu; Huang, Tsung-Wei; Ho, Tsung-Yi; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:47Z |
SECRET: Selective error correction for refresh energy reduction in DRAMs.
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Chen, Yi-Jung; Yang, Chia-Lin; Wang, Cheng-Yuan Michael; CHIA-LIN YANG; Shen, De-Yu; Lin, Chung-Hsiang; Lin, Chung-Hsiang;Shen, De-Yu;Chen, Yi-Jung;Yang, Chia-Lin;Wang, Cheng-Yuan Michael |
| 臺大學術典藏 |
2020-05-04T07:27:46Z |
Full system simulation framework for integrated CPU/GPU architecture.
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Wang, Po-Han;Liu, Gen-Hong;Yeh, Jen-Chieh;Chen, Tse-Min;Huang, Hsu-Yao;Yang, Chia-Lin;Liu, Shih-Lien;Greensky, James; Wang, Po-Han; Liu, Gen-Hong; Yeh, Jen-Chieh; Chen, Tse-Min; Huang, Hsu-Yao; Yang, Chia-Lin; Liu, Shih-Lien; Greensky, James; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:46Z |
DuraCache: a durable SSD cache using MLC NAND flash.
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Liu, Ren-Shuo;Yang, Chia-Lin;Li, Cheng-Hsuan;Chen, Geng-You; Liu, Ren-Shuo; Yang, Chia-Lin; Li, Cheng-Hsuan; Chen, Geng-You; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:46Z |
Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs.
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Lin, Ping-Sheng;Chen, Yi-Jung;Yang, Chia-Lin;Lu, Yi-Chang; Lin, Ping-Sheng; Chen, Yi-Jung; Yang, Chia-Lin; Lu, Yi-Chang; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:46Z |
Thermal coupling aware task migration using neighboring core search for many-core systems.
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Lu, Yi-Chang; Yang, Chia-Lin; CHIA-LIN YANG; Mizunuma, Hitoshi; Mizunuma, Hitoshi;Lu, Yi-Chang;Yang, Chia-Lin |
| 臺大學術典藏 |
2020-05-04T07:27:46Z |
Memory access aware power gating for MPSoCs.
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Lin, Ye-Jyun; Lin, Ye-Jyun;Yang, Chia-Lin;Huang, Jiao-Wei;Chang, Naehyuck; Yang, Chia-Lin; Huang, Jiao-Wei; Chang, Naehyuck; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:45Z |
Improving DRAM latency with dynamic asymmetric subarray.
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Lu, Shih-Lien;Lin, Ying-Chen;Yang, Chia-Lin; Lu, Shih-Lien; Lin, Ying-Chen; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:45Z |
A buffer cache architecture for smartphones with hybrid DRAM/PCM memory.
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CHIA-LIN YANG; Wang, Cheng-Yuan Michael; Li, Hsiang-Pang; Yang, Chia-Lin; Lin, Ye-Jyun; Lin, Ye-Jyun;Yang, Chia-Lin;Li, Hsiang-Pang;Wang, Cheng-Yuan Michael |
| 臺大學術典藏 |
2020-05-04T07:27:45Z |
NVM duet: unified working memory and persistent store architecture.
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Liu, Ren-Shuo;Shen, De-Yu;Yang, Chia-Lin;Yu, Shun-Chih;Wang, Cheng-Yuan Michael; Liu, Ren-Shuo; Shen, De-Yu; Yang, Chia-Lin; Yu, Shun-Chih; Wang, Cheng-Yuan Michael; CHIA-LIN YANG |
Showing items 1-50 of 190 (4 Page(s) Totally)
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