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Taiwan Academic Institutional Repository >
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"yang chia lin"
Showing items 31-55 of 190 (8 Page(s) Totally)
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| 臺大學術典藏 |
2020-05-04T07:27:49Z |
A progressive-ILP based routing algorithm for cross-referencing biochips.
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Yuh, Ping-Hung;Sapatnekar, Sachin S.;Yang, Chia-Lin;Chang, Yao-Wen; Yuh, Ping-Hung; Sapatnekar, Sachin S.; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:49Z |
Cache leakage control mechanism for hard real-time systems.
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Chi, Jaw-Wei;Yang, Chia-Lin;Chen, Yi-Jung;Chen, Jian-Jia; Chi, Jaw-Wei; Yang, Chia-Lin; Chen, Yi-Jung; Chen, Jian-Jia; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:49Z |
BioRoute: a network-flow based routing algorithm for digital microfluidic biochips.
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Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:49Z |
3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design.
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Chien, Shao-Yi; Shih, Chi-Sheng; Ku, Mong-Kai; Yang, Chia-Lin; Chang, Yao-Wen; Kuo, Tei-Wei; Chen, Liang-Gee; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:48Z |
Hierarchical memory scheduling for multimedia MPSoCs.
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Lin, Ye-Jyun;Yang, Chia-Lin;Lin, Tay-Jyi;Huang, Jiao-Wei;Chang, Naehyuck; Lin, Ye-Jyun; Yang, Chia-Lin; Lin, Tay-Jyi; Huang, Jiao-Wei; Chang, Naehyuck; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:48Z |
Parallelization and characterization of GARCH option pricing on GPUs.
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Liu, Ren-Shuo;Tsai, Yun-Cheng;Yang, Chia-Lin; Liu, Ren-Shuo; Tsai, Yun-Cheng; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:48Z |
Memory Latency Reduction via Thread Throttling.
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Cheng, Hsiang-Yun;Lin, Chung-Hsiang;Li, Jian;Yang, Chia-Lin; Cheng, Hsiang-Yun; Lin, Chung-Hsiang; Li, Jian; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:48Z |
Thermal modeling for 3D-ICs with integrated microchannel cooling.
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Lu, Yi-Chang; Yang, Chia-Lin; Mizunuma, Hitoshi;Yang, Chia-Lin;Lu, Yi-Chang; Mizunuma, Hitoshi; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:47Z |
Optimizing NAND flash-based SSDs via retention relaxation.
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Liu, Ren-Shuo; Yang, Chia-Lin; Wu, Wei; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:47Z |
Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs.
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Chen, Yi-Jung; Yang, Chia-Lin; Chen, Jian-Jia; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:47Z |
A SAT-based routing algorithm for cross-referencing biochips.
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Yuh, Ping-Hung;Lin, Cliff Chiung-Yu;Huang, Tsung-Wei;Ho, Tsung-Yi;Yang, Chia-Lin;Chang, Yao-Wen; Yuh, Ping-Hung; Lin, Cliff Chiung-Yu; Huang, Tsung-Wei; Ho, Tsung-Yi; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:47Z |
SECRET: Selective error correction for refresh energy reduction in DRAMs.
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Chen, Yi-Jung; Yang, Chia-Lin; Wang, Cheng-Yuan Michael; CHIA-LIN YANG; Shen, De-Yu; Lin, Chung-Hsiang; Lin, Chung-Hsiang;Shen, De-Yu;Chen, Yi-Jung;Yang, Chia-Lin;Wang, Cheng-Yuan Michael |
| 臺大學術典藏 |
2020-05-04T07:27:46Z |
Full system simulation framework for integrated CPU/GPU architecture.
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Wang, Po-Han;Liu, Gen-Hong;Yeh, Jen-Chieh;Chen, Tse-Min;Huang, Hsu-Yao;Yang, Chia-Lin;Liu, Shih-Lien;Greensky, James; Wang, Po-Han; Liu, Gen-Hong; Yeh, Jen-Chieh; Chen, Tse-Min; Huang, Hsu-Yao; Yang, Chia-Lin; Liu, Shih-Lien; Greensky, James; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:46Z |
DuraCache: a durable SSD cache using MLC NAND flash.
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Liu, Ren-Shuo;Yang, Chia-Lin;Li, Cheng-Hsuan;Chen, Geng-You; Liu, Ren-Shuo; Yang, Chia-Lin; Li, Cheng-Hsuan; Chen, Geng-You; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:46Z |
Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs.
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Lin, Ping-Sheng;Chen, Yi-Jung;Yang, Chia-Lin;Lu, Yi-Chang; Lin, Ping-Sheng; Chen, Yi-Jung; Yang, Chia-Lin; Lu, Yi-Chang; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:46Z |
Thermal coupling aware task migration using neighboring core search for many-core systems.
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Lu, Yi-Chang; Yang, Chia-Lin; CHIA-LIN YANG; Mizunuma, Hitoshi; Mizunuma, Hitoshi;Lu, Yi-Chang;Yang, Chia-Lin |
| 臺大學術典藏 |
2020-05-04T07:27:46Z |
Memory access aware power gating for MPSoCs.
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Lin, Ye-Jyun; Lin, Ye-Jyun;Yang, Chia-Lin;Huang, Jiao-Wei;Chang, Naehyuck; Yang, Chia-Lin; Huang, Jiao-Wei; Chang, Naehyuck; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:45Z |
Improving DRAM latency with dynamic asymmetric subarray.
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Lu, Shih-Lien;Lin, Ying-Chen;Yang, Chia-Lin; Lu, Shih-Lien; Lin, Ying-Chen; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:45Z |
A buffer cache architecture for smartphones with hybrid DRAM/PCM memory.
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CHIA-LIN YANG; Wang, Cheng-Yuan Michael; Li, Hsiang-Pang; Yang, Chia-Lin; Lin, Ye-Jyun; Lin, Ye-Jyun;Yang, Chia-Lin;Li, Hsiang-Pang;Wang, Cheng-Yuan Michael |
| 臺大學術典藏 |
2020-05-04T07:27:45Z |
NVM duet: unified working memory and persistent store architecture.
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Liu, Ren-Shuo;Shen, De-Yu;Yang, Chia-Lin;Yu, Shun-Chih;Wang, Cheng-Yuan Michael; Liu, Ren-Shuo; Shen, De-Yu; Yang, Chia-Lin; Yu, Shun-Chih; Wang, Cheng-Yuan Michael; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:45Z |
EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs.
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Liu, Ren-Shuo;Chuang, Meng-Yen;Yang, Chia-Lin;Li, Cheng-Hsuan;Ho, Kin-Chu;Li, Hsiang-Pang; Liu, Ren-Shuo; Chuang, Meng-Yen; Yang, Chia-Lin; Li, Cheng-Hsuan; Ho, Kin-Chu; Li, Hsiang-Pang; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:44Z |
Message from the general co-chairs.
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Garrett, David; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:44Z |
Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator.
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Wang, Li;Tsai, Ren-Wei;Wang, Shao-Chung;Chen, Kun-Chih;Wang, Po-Han;Cheng, Hsiang-Yun;Lee, Yi-Chung;Shu, Sheng-Jie;Yang, Chun-Chieh;Hsu, Min-Yih;Kan, Li-Chen;Lee, Chao-Lin;Yu, Tzu-Chieh;Peng, Rih-Ding;Yang, Chia-Lin;Hwang, Yuan-Shin;Lee, Jenq Kuen;Tsao, Shiao-Li;Ouhyoung, Ming; Wang, Li; Tsai, Ren-Wei; Wang, Shao-Chung; Chen, Kun-Chih; Wang, Po-Han; Cheng, Hsiang-Yun; Lee, Yi-Chung; Shu, Sheng-Jie; Yang, Chun-Chieh; Hsu, Min-Yih; Kan, Li-Chen; Lee, Chao-Lin; Yu, Tzu-Chieh; Peng, Rih-Ding; Yang, Chia-Lin; Hwang, Yuan-Shin; Lee, Jenq Kuen; Tsao, Shiao-Li; Ouhyoung, Ming; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:44Z |
Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture.
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Wang, Po-Han;Li, Cheng-Hsuan;Yang, Chia-Lin; Wang, Po-Han; Li, Cheng-Hsuan; Yang, Chia-Lin; CHIA-LIN YANG |
| 臺大學術典藏 |
2020-05-04T07:27:44Z |
MCSSim: A memory channel storage simulator.
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Chen, Renhai;Shao, Zili;Yang, Chia-Lin;Li, Tao; Chen, Renhai; Shao, Zili; Yang, Chia-Lin; Li, Tao; CHIA-LIN YANG |
Showing items 31-55 of 190 (8 Page(s) Totally)
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