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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
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Institution Date Title Author
臺大學術典藏 2020-05-04T07:27:06Z Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations. AI-CHUN PANG; Kuo, Tei-Wei; Pang, Ai-Chun; Yang, Chia-Lin; Chuang, Kai-Hsiang; Hsu, Heng-Ruey; Chen, Jian-Jia
臺大學術典藏 2018-09-10T07:37:14Z Thermal modeling for 3D-ICs with integrated microchannel cooling Mizunuma, Hitoshi;Yang, Chia-Lin;Lu, Yi-Chang; Mizunuma, Hitoshi; Yang, Chia-Lin; Lu, Yi-Chang; YI-CHANG LU
臺大學術典藏 2018-09-10T07:33:29Z Content-aware energy prediction for video streaming in mobile devices Li, Han-Lin; Yang, Chia-Lin; CHIA-LIN YANG; Shun, Chia-Tung; Li, Yi-Chan; Li, Hisu-Hsien; Li, Yi-Chan;Li, Hisu-Hsien;Li, Han-Lin;Yang, Chia-Lin
臺大學術典藏 2018-09-10T07:33:29Z A predictive shutdown technique for GPU shader processors Wang, Po-Han;Chen, Yen-Ming;Yang, Chia-Lin;Cheng, Yu-Jung; Wang, Po-Han; Chen, Yen-Ming; Yang, Chia-Lin; Cheng, Yu-Jung; CHIA-LIN YANG
臺大學術典藏 2018-09-10T07:30:37Z A multi-core architecture based parallel framework for h.264/avc deblocking filters Wang, Sung-Wen;Yang, Shu-Sian;Chen, Hong-Ming;Yang, Chia-Lin;Wu, Ja-Ling; Wang, Sung-Wen; Yang, Shu-Sian; Chen, Hong-Ming; Yang, Chia-Lin; Wu, Ja-Ling; JA-LING WU; CHIA-LIN YANG
臺大學術典藏 2018-09-10T07:03:50Z A progressive-ILP based routing algorithm for cross-referencing biochips Yuh, Ping-Hung; Sapatnekar, S.; Yang, Chia-Lin; Chang, Yao-Wen; YAO-WEN CHANG; CHIA-LIN YANG
臺大學術典藏 2018-09-10T07:03:49Z BioRoute: A network-flow-based routing algorithm for the synthesis of digital microfluidic biochips Yuh, Ping-Hung;Yang, Chia-Lin;Chang, Yao-Wen; Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; YAO-WEN CHANG; Yang, Chia-Lin
臺大學術典藏 2018-09-10T07:00:36Z Energy-aware flash memory management in virtual memory system Li, Han-Lin;Yang, Chia-Lin;Tseng, Hung-Wei; Li, Han-Lin; Yang, Chia-Lin; Tseng, Hung-Wei; CHIA-LIN YANG
臺大學術典藏 2018-09-10T07:00:36Z Exploiting instruction level parallelism in geometry processing for three dimensional graphics applications Yang, Chia-Lin; Sano, Barton; Lebeck, Alvin R.; CHIA-LIN YANG
臺大學術典藏 2018-09-10T07:00:35Z Tunablevp: a tunable virtual platform for easy soc design space exploration Lin, Ye-Jyun; Chen, Yi-Jung; Huang, Chin-Chie; Lin, Tzu-Ching; Chi, Jaw-Wei; Yang, Chia-Lin; CHIA-LIN YANG
臺大學術典藏 2018-09-10T06:31:00Z Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; Yang, Chia-Lin
臺大學術典藏 2018-09-10T06:30:59Z Temporal floorplanning using the three-dimensional transitive closure subGraph Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; Yang, Chia-Lin
臺大學術典藏 2018-09-10T06:27:37Z An architectural co-synthesis algorithm for energy-aware network-on-chip design Hung, Wei-Hsuan;Chen, Yi-Jung;Yang, Chia-Lin;Chang, Yen-Sheng;Su, Alan P.; Hung, Wei-Hsuan; Chen, Yi-Jung; Yang, Chia-Lin; Chang, Yen-Sheng; Su, Alan P.; CHIA-LIN YANG
臺大學術典藏 2018-09-10T05:20:41Z Reconfigurable platform for content science research Shih, C.-S.; Yang, C.-L.; Ku, M.-K.; Kuo, T.-W.; Chien, S.-Y.; Chang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN; Shih, Chi-Sheng; Yang, Chia-Lin; TEI-WEI KUO; YAO-WEN CHANG; SHAO-YI CHIEN
臺大學術典藏 2018-09-10T05:18:22Z Software-controlled cache architecture for energy efficiency Yang, Chia-Lin;Tseng, Hung-Wei;Ho, Chia-Chiang;Wu, Ja-Ling; Yang, Chia-Lin; Tseng, Hung-Wei; Ho, Chia-Chiang; Wu, Ja-Ling; JA-LING WU; Yang, Chia-Lin
臺大學術典藏 2018-09-10T04:31:08Z Smart cache: An energy-efficient D-cache for a software MPEG-2 video decoder Yang, Chia-Lin;Tseng, Hung-Wei;Ho, Chia-Chiang; Yang, Chia-Lin; Tseng, Hung-Wei; Ho, Chia-Chiang; CHIA-LIN YANG
臺大學術典藏 2018-09-10T03:28:17Z Push vs. pull: Data movement for linked data structures Yang, Chia-Lin; Lebeck, Alvin R.; CHIA-LIN YANG
國立交通大學 2018-08-21T05:57:06Z Analyzing OpenCL 2.0 Workloads Using a Heterogeneous CPU-GPU Simulator Wang, Li; Tsai, Ren-Wei; Wang, Shao-Chung; Chen, Kun-Chih; Wang, Po-Han; Cheng, Hsiang-Yun; Lee, Yi-Chung; Shu, Sheng-Jie; Yang, Chun-Chieh; Hsu, Min-Yih; Kan, Li-Chen; Lee, Chao-Lin; Yu, Tzu-Chieh; Peng, Rih-Ding; Yang, Chia-Lin; Hwang, Yuan-Shin; Lee, Jenq-Kuen; Tsao, Shiao-Li; Ouhyoung, Ming
臺大學術典藏 2018-07-05T01:59:29Z A Space-Efficient Caching Mechanism for Flash-Memory Address Translation Yang, Chia-Lin; Kuo, Tei-Wei; Wu, Chin-Hsien; Wu, Chin-Hsien; Kuo, Tei-Wei; Yang, Chia-Lin
臺大學術典藏 2018-07-05T01:55:22Z Tolerating Memory Latency Through Push Prefetching for Pointer-Intensive Applications Lee, Chien-Hao; Tseng, Hung-Wei; Lebeck, Alvin R.; Yang, Chia-Lin; Lebeck, Alvin R.; Tseng, Hung-Wei; Lee, Chien-Hao; Yang, Chia-Lin
臺大學術典藏 2018-07-05T01:53:24Z Hierarchical Value Cache Encoding for Off-Chip Data Bus King, Ku-Jei; Yang, Chia-Lin; Lin, Chung-Hsiang; Lin, Chung-Hsiang; Yang, Chia-Lin; King, Ku-Jei
臺大學術典藏 2018 DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning. Li, Hsiang-Pang; Chang, Meng-Fan; CHIA-LIN YANG; Chang, Hung-Sheng; Lin, Meng-Yao;Cheng, Hsiang-Yun;Lin, Wei-Ting;Yang, Tzu-Hsien;Tseng, I-Ching;Yang, Chia-Lin;Hu, Han-Wen;Chang, Hung-Sheng;Li, Hsiang-Pang;Chang, Meng-Fan; Lin, Meng-Yao; Cheng, Hsiang-Yun; Lin, Wei-Ting; Yang, Tzu-Hsien; Tseng, I-Ching; Yang, Chia-Lin; Hu, Han-Wen
國立交通大學 2017-04-21T06:56:47Z Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality Liu, Ren-Shuo; Chuang, Meng-Yen; Yang, Chia-Lin; Li, Cheng-Hsuan; Ho, Kin-Chu; Li, Hsiang-Pang
臺大學術典藏 2017 Recap of the 2017 International Symposium on Low Power Electronics and Design (ISLPED) CHIA-LIN YANG; Garrett, David; Yang, Chia-Lin
國立成功大學 2016-10 Effect of annealing temperature on the optoelectronic characteristic of Al and Ga co-doping ZnO thin films Tsai, Tang-Yi; Chen, Tao-Hsing; Tu, Sheng-Lung; Su, Yen-Hsun; Shen, Yun-Hwei; Yang, Chia-Lin

Showing items 66-90 of 190  (8 Page(s) Totally)
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