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Showing items 21-39 of 39  (2 Page(s) Totally)
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Institution Date Title Author
國立交通大學 2014-12-16T06:13:50Z Static random access memory with ripple bit lines/search lines for improving current leakage/variation tolerance and density/performance Chuang Ching-Te; Yang Hao-I; Lu Chien-Yu; Chen Chien-Hen; Chang Chi-Shin; Huang Po-Tsang; Lai Shu-Lin; Hwang Wei; Jou Shyh-Jye; Tu Ming-Hsien
國立交通大學 2014-12-16T06:13:49Z Oscillato based on a 6T SRAM for measuring the bias temperature instability Chuang Ching-Te; Jou Shyh-Jye; Hwang Wei; Tsai Ming-Chien; Lin Yi-Wei; Yang Hao-I; Tu Ming-Hsien; Shih Wei-Chiang; Lien Nan-Chun; Lee Kuen-Di
國立交通大學 2014-12-16T06:13:47Z Static random access memory apparatus and bit-line voltage controller thereof Chuang Ching-Te; Lien Nan-Chun; Liao Wei-Nan; Chang Chi-Hsin; Yang Hao-I; Hwang Wei; Tu Ming-Hsien
國立交通大學 2014-12-12T01:23:24Z 高可靠度奈米級靜態隨機存取記憶體設計: 可靠度分析與改善技術 楊皓義; Yang, Hao-I; 黃威; Hwang, Wei
國立交通大學 2014-12-08T15:37:44Z Impacts of gate-oxide breakdown on power-gated SRAM Yang, Hao-I; Hwang, Wei; Chuang, Ching-Te
國立交通大學 2014-12-08T15:35:45Z A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist Chang, Chi-Shin; Yang, Hao-I; Liao, Wei-Nan; Lin, Yi-Wei; Lien, Nan-Chun; Chen, Chien-Hen; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Tu, Ming-Hsien; Huang, Huan-Shun; Hu, Yong-Jyun; Kan, Paul-Sen; Cheng, Cheng-Yo; Wang, Wei-Chang; Wang, Jian-Hao; Lee, Kuen-Di; Chen, Chia-Cheng; Shih, Wei-Chiang
國立交通大學 2014-12-08T15:33:15Z Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM Yang, Hao-I.; Yang, Shyh-Chyi; Hwang, Wei; Chuang, Ching-Te
國立交通大學 2014-12-08T15:31:09Z Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices Yang, Hao-I; Hwang, Wei; Chuang, Ching-Te
國立交通大學 2014-12-08T15:30:06Z High-Performance 0.6V V-MIN 55nm 1.0Mb 6T SRAM with Adaptive BL Bleeder Yang, Hao-I; Lin, Yi-Wei; Hsia, Mao-Chih; Lin, Geng-Cing; Chang, Chi-Shin; Chen, Yin-Nien; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Lien, Nan-Chun; Li, Hung-Yu; Lee, Kuen-Di; Shih, Wei-Chiang; Wu, Ya-Ping; Lee, Wen-Ta; Hsu, Chih-Chiang
國立交通大學 2014-12-08T15:29:40Z A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist Lu, Chien-Yu; Tu, Ming-Hsien; Yang, Hao-I; Wu, Ya-Ping; Huang, Huan-Shun; Lin, Yuh-Jiun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei
國立交通大學 2014-12-08T15:25:40Z TIMING CONTROL DEGRADATION AND NBTI/PBTI TOLERANT DESIGN FOR WRITE-REPLICA CIRCUIT IN NANOSCALE CMOS SRAM Yang, Shyh-Chyi; Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei
國立交通大學 2014-12-08T15:25:25Z A MICRO-WATT MULTI-PORT REGISTER FILE WITH WIDE OPERATING VOLTAGE RANGE Yang, Shyh-Chyi; Yang, Hao-I; Hwang, Wei
國立交通大學 2014-12-08T15:25:24Z Impacts of Contact Resistance and NBTI/PBTI on SRAM with High-kappa Metal-Gate Devices Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei
國立交通大學 2014-12-08T15:25:19Z Impact of Gate-Oxide Breakdown on Power-Gated SRAM Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei
國立交通大學 2014-12-08T15:23:36Z Impacts of NBTI and PBTI on Power-Gated SRAM with High-k Metal-Gate Devices Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei
國立交通大學 2014-12-08T15:21:19Z A High-Performance Low V(MIN) 55nm 512Kb Disturb-Free 8T SRAM with Adaptive VVSS Control Yang, Hao-I; Yang, Shih-Chi; Hsia, Mao-Chih; Lin, Yung-Wei; Lin, Yi-Wei; Chen, Chien-Hen; Chang, Chi-Shin; Lin, Geng-Cing; Chen, Yin-Nien; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Lien, Nan-Chun; Li, Hung-Yu; Lee, Kuen-Di; Shih, Wei-Chiang; Wu, Ya-Ping; Lee, Wen-Ta; Hsu, Chih-Chiang
國立交通大學 2014-12-08T15:20:11Z Impacts of NBTI on SRAM Array with Power Gating Structure Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei
國立交通大學 2014-12-08T15:02:14Z A controllable low-power dual-port embedded SRAM for DSP processor Yang, Hao-I; Chang, Ming-Hung; Lin, Tay-Jyi; Ou, Shih-Hao; Deng, Siang-Sen; Liu, Chih-Wei; Hwang, Wei
國立成功大學 2005-06-29 動態可重新架構化之超純量處理器設計 楊皓義; Yang, Hao-I

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