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Showing items 36-39 of 39 (2 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:21:19Z |
A High-Performance Low V(MIN) 55nm 512Kb Disturb-Free 8T SRAM with Adaptive VVSS Control
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Yang, Hao-I; Yang, Shih-Chi; Hsia, Mao-Chih; Lin, Yung-Wei; Lin, Yi-Wei; Chen, Chien-Hen; Chang, Chi-Shin; Lin, Geng-Cing; Chen, Yin-Nien; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Lien, Nan-Chun; Li, Hung-Yu; Lee, Kuen-Di; Shih, Wei-Chiang; Wu, Ya-Ping; Lee, Wen-Ta; Hsu, Chih-Chiang |
| 國立交通大學 |
2014-12-08T15:20:11Z |
Impacts of NBTI on SRAM Array with Power Gating Structure
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Yang, Hao-I; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2014-12-08T15:02:14Z |
A controllable low-power dual-port embedded SRAM for DSP processor
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Yang, Hao-I; Chang, Ming-Hung; Lin, Tay-Jyi; Ou, Shih-Hao; Deng, Siang-Sen; Liu, Chih-Wei; Hwang, Wei |
| 國立成功大學 |
2005-06-29 |
動態可重新架構化之超純量處理器設計
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楊皓義; Yang, Hao-I |
Showing items 36-39 of 39 (2 Page(s) Totally)
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