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Showing items 1-6 of 6 (1 Page(s) Totally)
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| 臺大學術典藏 |
2018-07-06T09:46:46Z |
A new pipelined adaptive DFE architecture with improved convergence rate
|
Wu, An-Yeu; Yang, Meng-Da; Yang, Meng-Da; Wu, An-Yeu |
| 國立臺灣大學 |
2004 |
Fast Convergent Pipelined Adaptive DFE Architecture Using Post-Cursor Processing Filter Technique
|
Yang, Meng-Da; Wu, An-Yeu; Lai, Jyh-Ting |
| 國立臺灣大學 |
2004 |
High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme
|
Yang, Meng-Da; Wu, An-Yeu; Lai, Jyh-Ting |
| 國立臺灣大學 |
2002-10 |
High-performance adaptive decision feedback equalizer based on predictive parallel branch slicer scheme
|
Yang, Meng-Da; Wu, An-Yeu |
| 臺大學術典藏 |
2002-10 |
High-performance adaptive decision feedback equalizer based on predictive parallel branch slicer scheme
|
Yang, Meng-Da; Wu, An-Yeu; Yang, Meng-Da; Wu, An-Yeu |
| 國立臺灣大學 |
2002-05 |
A new pipelined adaptive DFE architecture with improved convergence rate
|
Yang, Meng-Da; Wu, An-Yeu |
Showing items 1-6 of 6 (1 Page(s) Totally)
1
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