|
English
|
正體中文
|
简体中文
|
Total items :2822924
|
|
Visitors :
30056044
Online Users :
1028
Project Commissioned by the Ministry of Education Project Executed by National Taiwan University Library
|
|
|
Taiwan Academic Institutional Repository >
Browse by Author
|
"yang rong jyi"
Showing items 1-10 of 12 (2 Page(s) Totally) 1 2 > >> View [10|25|50] records per page
國立臺灣大學 |
2008-02 |
An all-digital fast-locking programmable DLL-based clock generator
|
Liang, Chuan-Kang; Yang, Rong-Jyi; Liu, Shen-Iuan |
國立臺灣大學 |
2008 |
An All-Digital Fast-Locking Programmable DLL-Based Clock Generator
|
Liang, Chuan-Kang; Yang, Rong-Jyi; Liu, Shen-Iuan |
國立臺灣大學 |
2007 |
A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
國立臺灣大學 |
2007 |
A 2.5GHz all-digital delay-locked loop in 0.13μm CMOS technology
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
國立臺灣大學 |
2006 |
運用於有線傳送接收機之CMOS時脈產生及時脈資料回復電路的設計與實現
|
楊榮吉; Yang, Rong-Jyi |
國立臺灣大學 |
2006 |
A 200-Mbps∼ 2-Gbps continuous-rate clock-and-data-recovery circuit
|
Yang, Rong-Jyi; Chao, Kuan-Hua; Liu, Shen-Iuan |
國立臺灣大學 |
2006 |
A 155.52 Mbps–3.125 Gbps Continuous-Rate Clock and Data Recovery Circuit
|
Yang, Rong-Jyi; Chao, Kuan-Hua; Hwu, Sy-Chyuan; Liang, Chuan-Kang; Liu, Shen-Iuan |
國立臺灣大學 |
2005 |
A wide-range multiphase delay-locked loop using mixed-mode VCDLs
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
國立臺灣大學 |
2005 |
A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
國立臺灣大學 |
2004-08 |
A 1.7~3.125Gbps clock and data recovery circuit using a gated frequency detector
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
Showing items 1-10 of 12 (2 Page(s) Totally) 1 2 > >> View [10|25|50] records per page
|