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Showing items 1-12 of 12 (1 Page(s) Totally)
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| 國立臺灣大學 |
2008-02 |
An all-digital fast-locking programmable DLL-based clock generator
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Liang, Chuan-Kang; Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2008 |
An All-Digital Fast-Locking Programmable DLL-Based Clock Generator
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Liang, Chuan-Kang; Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2007 |
A 2.5GHz all-digital delay-locked loop in 0.13μm CMOS technology
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Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2006 |
運用於有線傳送接收機之CMOS時脈產生及時脈資料回復電路的設計與實現
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楊榮吉; Yang, Rong-Jyi |
| 國立臺灣大學 |
2006 |
A 200-Mbps∼ 2-Gbps continuous-rate clock-and-data-recovery circuit
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Yang, Rong-Jyi; Chao, Kuan-Hua; Liu, Shen-Iuan |
| 國立臺灣大學 |
2006 |
A 155.52 Mbps–3.125 Gbps Continuous-Rate Clock and Data Recovery Circuit
|
Yang, Rong-Jyi; Chao, Kuan-Hua; Hwu, Sy-Chyuan; Liang, Chuan-Kang; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005 |
A wide-range multiphase delay-locked loop using mixed-mode VCDLs
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Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005 |
A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector
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Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004-08 |
A 1.7~3.125Gbps clock and data recovery circuit using a gated frequency detector
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Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
A 3.125-Gb/s Clock and Data Recovery Circuit for the 10-Gbase-LX4 Ethernet
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Yang, Rong-Jyi; Chen, Shang-Ping; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection
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Chang, Hsiang-Hui; Yang, Rong-Jyi; Liu, Shen-Iuan |
Showing items 1-12 of 12 (1 Page(s) Totally)
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