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Showing items 1-7 of 7 (1 Page(s) Totally)
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| 臺大學術典藏 |
2018-09-10T03:43:43Z |
Hardware-efficient architecture design of tree-depth scanning and multiple quantization scheme for MPEG-4 still texture coding
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Chang, Hao-Chieh; Yang, Zhong-Lan; Lian, Chung-Jr; Chen, Liang-Gee; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T03:25:55Z |
Programmable VLSI architecture for 2-D discrete wavelet transform
|
Chen, Liang-Gee; LIANG-GEE CHEN; Chen, Chien-Yu; Yang, Zhong-Lan; Wang, Tu-Chih |
| 國立臺灣大學 |
2003 |
Hardware-Efficient Architecture Design for Zerotree Coding in MPEG-4 Still Texture Coder
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Lian, Chung-Jr; Yang, Zhong-Lan; Chang, Hao-Chieh; Chen, Liang-Gee |
| 國立臺灣大學 |
2001-05 |
Hardware-efficient architecture design of tree-depth scanning and multiple quantization scheme for MPEG-4 still texture coding
|
Chang, Hao-Chieh; Yang, Zhong-Lan; Lian, Chung-Jr; Chen, Liang-Gee |
| 國立臺灣大學 |
2001 |
A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform
|
Chen, Chien-Yu; Yang, Zhong-Lan; Wang, Tu-Chih; Chen, Liang-Gee |
| 國立臺灣大學 |
2000-05 |
A programmable VLSI architecture for 2-D discrete wavelet transform
|
Chen, Chien-Yu; Yang, Zhong-Lan; Wang, Tu-Chih; Chen, Liang-Gee |
| 臺大學術典藏 |
2000-05 |
A programmable VLSI architecture for 2-D discrete wavelet transform
|
Chen, Chien-Yu; Yang, Zhong-Lan; Wang, Tu-Chih; Chen, Liang-Gee; Chen, Chien-Yu; Yang, Zhong-Lan; Wang, Tu-Chih; Chen, Liang-Gee |
Showing items 1-7 of 7 (1 Page(s) Totally)
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