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Showing items 136-185 of 348 (7 Page(s) Totally)
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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T08:42:37Z	PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs	Chuang, Y.-L.;Lin, H.-T.;Ho, T.-Y.;Chang, Y.-W.;Marculescu, D.; Chuang, Y.-L.; Lin, H.-T.; Ho, T.-Y.; Chang, Y.-W.; Marculescu, D.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:42:37Z	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems: Guest Editorial	Saxena, P.;Chang, Y.-W.; Saxena, P.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:42:36Z	Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs	Chuang, Y.-L.;Lee, P.-W.;Chang, Y.-W.; Chuang, Y.-L.; Lee, P.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:42:36Z	TSV-aware analytical placement for 3D IC designs	Hsu, M.-K.;Chang, Y.-W.;Balabanov, V.; Hsu, M.-K.; Chang, Y.-W.; Balabanov, V.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:42:36Z	Timing ECO optimization via B?zier curve smoothing and fixability identification	Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:42:36Z	Thermal-driven analog placement considering device matching	YAO-WEN CHANG; Chang, Y.-W.; Wong, M.D.F.; Lin, M.P.-H.; Zhang, H.; Lin, M.P.-H.;Zhang, H.;Wong, M.D.F.;Chang, Y.-W.
臺大學術典藏	2018-09-10T08:42:36Z	Simultaneous layout migration and decomposition for double patterning technology	Hsu, C.-H.;Chang, Y.-W.;Nassif, S.R.; Hsu, C.-H.; Chang, Y.-W.; Nassif, S.R.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:39:31Z	A SAT-based routing algorithm for cross-referencing biochips	Yuh, P.-H.;Lin, C.C.-Y.;Huang, T.-W.;Ho, T.-Y.;Yang, C.-L.;Chang, Y.-W.; Yuh, P.-H.; Lin, C.C.-Y.; Huang, T.-W.; Ho, T.-Y.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; CHIA-LIN YANG
臺大學術典藏	2018-09-10T08:19:13Z	TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders	Kuan-Hsien Ho;Jie-Hong R. Jiang;Yao-Wen Chang; Kuan-Hsien Ho; Jie-Hong R. Jiang; Yao-Wen Chang; YAO-WEN CHANG; JIE-HONG JIANG
臺大學術典藏	2018-09-10T08:17:03Z	Effect of Broken Symmetry on the First Hyperpolarizability of a Centrosymmetric Molecule with an Application to Furan-Containing [2.2]Cyclophandiene	Yao-Wen Chang;Bih-Yaw Jin; Yao-Wen Chang; Bih-Yaw Jin; Chang, Yao-Wen; BIH-YAW JIN
臺大學術典藏	2018-09-10T08:14:58Z	ECO timing optimization using spare cells and technology remapping	Ho, K.-H.; Chen, Y.-P.; Fang, J.-W.; Chang, Y.-W.; Ho, K.-H.; Chen, Y.-P.; Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:58Z	Design-hierarchy aware mixed-size placement for routability optimization	Chuang, Y.-L.; Nam, G.-J.; Alpert, C.J.; Chang, Y.-W.; Roy, J.; Viswanathan, N.; Chuang, Y.-L.; Nam, G.-J.; Alpert, C.J.; Chang, Y.-W.; Roy, J.; Viswanathan, N.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:58Z	Density gradient minimization with coupling-constrained dummy fill for CMP control	Chen, H.-Y.; Chou, S.-J.; Chang, Y.-W.; Chen, H.-Y.; Chou, S.-J.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:58Z	Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips	Lin, C.C.-Y.; Chang, Y.-W.; Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:58Z	Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization	Shih, X.-W.; Cheng, C.-C.; Ho, Y.-K.; Chang, Y.-W.; Shih, X.-W.; Cheng, C.-C.; Ho, Y.-K.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:58Z	Area-I/O flip-chip routing for chip-package co-design considering signal skews	Fang, J.-W.; Chang, Y.-W.; Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:57Z	Predictive formulae for OPC with applications to lithography-friendly routing	Chen, T.-C.; Liao, G.-W.; Chang, Y.-W.; Chen, T.-C.; Liao, G.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:57Z	Native-conflict-aware wire perturbation for double patterning technology	Chen, S.-Y.;Chang, Y.-W.; Chen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:57Z	Multilayer global routing with via and wire capacity considerations	Hsu, C.-H.; Chen, H.-Y.; Chang, Y.-W.; Hsu, C.-H.; Chen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:57Z	ILP-based pin-count aware design methodology for microfluidic biochips	Lin, C.C.-Y.; Chang, Y.-W.; Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:57Z	High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees	Shiht, X.-W.; Leet, H.-C.; Hot, K.-H.; Chang, Y.-W.; Shiht, X.-W.; Leet, H.-C.; Hot, K.-H.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:57Z	Fast timing-model independent buffered clock-tree synthesis	Shih, X.-W.; Chang, Y.-W.; Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:57Z	Efficient provably good OPC modeling and its applications to interconnect optimization	Huang, S.-L.; Lin, C.-W.; Chang, Y.-W.; Huang, S.-L.; Lin, C.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:56Z	Unified analytical global placement for large-scale mixed-size circuit designs	Hsu, M.-K.;Chang, Y.-W.; Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:56Z	Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis	Falkenstern, P.; Xie, Y.; Chang, Y.-W.; Wang, Y.; YAO-WEN CHANG; Falkenstern, P.;Xie, Y.;Chang, Y.-W.;Wang, Y.
臺大學術典藏	2018-09-10T08:14:56Z	Template-mask design methodology for double patterning technology	Hsu, C.-H.;Chang, Y.-W.;Nassif, S.R.; Hsu, C.-H.; Chang, Y.-W.; Nassif, S.R.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:56Z	Redundant-wires-aware ECO timing and mask cost optimization	Fang, S.-Y.; Chien, T.-F.; Chang, Y.-W.; Fang, S.-Y.; Chien, T.-F.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T08:14:56Z	Pulsed-latch aware placement for timing-integrity optimization	Chuang, Y.-L.; Kim, S.; Shin, Y.; Chang, Y.-W.; Chuang, Y.-L.; Kim, S.; Shin, Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:58Z	Generic universal switch blocks	Shyu, Michael; Chang, Yu-Dong; Wu, Guang-Ming; Chang, Yao-Wen; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:58Z	Clustering- and probability-based approach for time-multiplexed FPGA partitioning	Chang, Yao-Wen; YAO-WEN CHANG; Jiang, Iris Hui-Ru; Chao, Mango Chia-Tso; Wu, Guang-Ming
臺大學術典藏	2018-09-10T07:36:57Z	An efficient pre-assignment routing algorithm for flip-chip designs	Lee, P.-W.;Lin, C.-W.;Chang, Y.-W.;Shen, C.-F.;Tseng, W.-C.; Lee, P.-W.; Lin, C.-W.; Chang, Y.-W.; Shen, C.-F.; Tseng, W.-C.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:57Z	A progressive-ILP-based routing algorithm for the synthesis of cross-referencing biochips	Yuh, P.-H.;Sapatnekar, S.S.;Yang, C.-L.;Chang, Y.-W.; Yuh, P.-H.; Sapatnekar, S.S.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; CHIA-LIN YANG
臺大學術典藏	2018-09-10T07:36:57Z	A novel wire-density-driven full-chip routing system for cmp variation control	Chen, H.-Y.;Chou, S.-J.;Wang, S.-L.;Chang, Y.-W.; Chen, H.-Y.; Chou, S.-J.; Wang, S.-L.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:57Z	A novel wire-density-driven full-chip routing system for CMP variation control	Chen, H.-Y.;Chou, S.-J.;Wang, S.-L.;Chang, Y.-W.; Chen, H.-Y.; Chou, S.-J.; Wang, S.-L.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:57Z	A novel hot-electron programming method in a buried diffusion bit-line SONOS memory by utilizing nonequilibrium charge transport	Wang, T.;Tang, C.-J.;Li, C.-W.;Lee, C.-H.;Ou, T.-F.;Chang, Y.-W.;Tsai, W.-J.;Lu, T.-C.;Chen, K.-C.;Lu, C.-Y.; Wang, T.; Tang, C.-J.; Li, C.-W.; Lee, C.-H.; Ou, T.-F.; Chang, Y.-W.; Tsai, W.-J.; Lu, T.-C.; Chen, K.-C.; Lu, C.-Y.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:57Z	Quasi-universal switch matrices for FPD design	Wu, G.-M.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:56Z	BIST design optimization for large-scale embedded memory cores	Chien, T.-F.;Chao, W.-C.;Li, C.-M.;Chang, Y.-W.;Liao, K.-Y.;Chang, M.-T.;Tsai, M.-H.;Tseng, C.-M.; Chien, T.-F.; Chao, W.-C.; Li, C.-M.; Chang, Y.-W.; Liao, K.-Y.; Chang, M.-T.; Tsai, M.-H.; Tseng, C.-M.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:56Z	Analog placement based on symmetry-island formulation	Lin, P.-H.;Chang, Y.-W.;Lin, S.-C.; Lin, P.-H.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:56Z	Analog placement based on symmetry-Island formulation	Lin, P.-H.;Chang, Y.-W.;Lin, S.-C.; Lin, P.-H.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:56Z	Analog layout synthesis - Recent advances in topological approaches	Graeb, H.;Balasa, F.;Castro-Lopez, R.;Chang, Y.-W.;Fern;ez, F.V.;Lin, P.-H.;Strasser, M.; Graeb, H.; Balasa, F.; Castro-Lopez, R.; Chang, Y.-W.; Fern; ez, F.V.; Lin, P.-H.; Strasser, M.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:55Z	ILP-based pin-count aware design methodology for microfluidic biochips	Lin, C.C.-Y.;Chang, Y.-W.; Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:55Z	High-performance global routing with fast overflow reduction	YAO-WEN CHANG; Qien, H.-Y.;Hsu, C.-H.;Chang, Y.-W.; Qien, H.-Y.; Hsu, C.-H.; Chang, Y.-W.
臺大學術典藏	2018-09-10T07:36:55Z	Floorplanning	Chen, T.-C.;Chang, Y.-W.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:55Z	Essential issues in analytical placement algorithms	Chang, Y.-W.;Jiang, Z.-W.;Chen, T.-C.; Chang, Y.-W.; Jiang, Z.-W.; Chen, T.-C.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:54Z	Thermal-driven analog placement considering device matching	Lin, P.-H.;Zhang, H.;Wong, M.D.F.;Chang, Y.-W.; Lin, P.-H.; Zhang, H.; Wong, M.D.F.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:54Z	T-trees: A tree-based representation for temporal and three-dimensional floorplanning	Yuh, P.-H.;Yang, C.-L.;Chang, Y.-W.; Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; CHIA-LIN YANG
臺大學術典藏	2018-09-10T07:36:54Z	Spare-cell-aware multilevel analytical placement	Jiang, Z.-W.;Hsu, M.-K.;Chang, Y.-W.;Chao, K.-Y.; Jiang, Z.-W.; Hsu, M.-K.; Chang, Y.-W.; Chao, K.-Y.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:54Z	Simultaneous layout migration and decomposition for double patterning technology	Hsu, C.-H.;Chang, Y.-W.;Nassif, S.R.; Hsu, C.-H.; Chang, Y.-W.; Nassif, S.R.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:54Z	Routing for manufacturability and reliability	Chen, H.-Y.;Chang, Y.-W.; Chen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:54Z	Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs	Lee, W.-P.;Marculescu, D.;Chang, Y.-W.; Lee, W.-P.; Marculescu, D.; Chang, Y.-W.; YAO-WEN CHANG

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