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Showing items 166-190 of 348 (14 Page(s) Totally)
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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T07:36:57Z	An efficient pre-assignment routing algorithm for flip-chip designs	Lee, P.-W.;Lin, C.-W.;Chang, Y.-W.;Shen, C.-F.;Tseng, W.-C.; Lee, P.-W.; Lin, C.-W.; Chang, Y.-W.; Shen, C.-F.; Tseng, W.-C.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:57Z	A progressive-ILP-based routing algorithm for the synthesis of cross-referencing biochips	Yuh, P.-H.;Sapatnekar, S.S.;Yang, C.-L.;Chang, Y.-W.; Yuh, P.-H.; Sapatnekar, S.S.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; CHIA-LIN YANG
臺大學術典藏	2018-09-10T07:36:57Z	A novel wire-density-driven full-chip routing system for cmp variation control	Chen, H.-Y.;Chou, S.-J.;Wang, S.-L.;Chang, Y.-W.; Chen, H.-Y.; Chou, S.-J.; Wang, S.-L.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:57Z	A novel wire-density-driven full-chip routing system for CMP variation control	Chen, H.-Y.;Chou, S.-J.;Wang, S.-L.;Chang, Y.-W.; Chen, H.-Y.; Chou, S.-J.; Wang, S.-L.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:57Z	A novel hot-electron programming method in a buried diffusion bit-line SONOS memory by utilizing nonequilibrium charge transport	Wang, T.;Tang, C.-J.;Li, C.-W.;Lee, C.-H.;Ou, T.-F.;Chang, Y.-W.;Tsai, W.-J.;Lu, T.-C.;Chen, K.-C.;Lu, C.-Y.; Wang, T.; Tang, C.-J.; Li, C.-W.; Lee, C.-H.; Ou, T.-F.; Chang, Y.-W.; Tsai, W.-J.; Lu, T.-C.; Chen, K.-C.; Lu, C.-Y.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:57Z	Quasi-universal switch matrices for FPD design	Wu, G.-M.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:56Z	BIST design optimization for large-scale embedded memory cores	Chien, T.-F.;Chao, W.-C.;Li, C.-M.;Chang, Y.-W.;Liao, K.-Y.;Chang, M.-T.;Tsai, M.-H.;Tseng, C.-M.; Chien, T.-F.; Chao, W.-C.; Li, C.-M.; Chang, Y.-W.; Liao, K.-Y.; Chang, M.-T.; Tsai, M.-H.; Tseng, C.-M.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:56Z	Analog placement based on symmetry-island formulation	Lin, P.-H.;Chang, Y.-W.;Lin, S.-C.; Lin, P.-H.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:56Z	Analog placement based on symmetry-Island formulation	Lin, P.-H.;Chang, Y.-W.;Lin, S.-C.; Lin, P.-H.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:56Z	Analog layout synthesis - Recent advances in topological approaches	Graeb, H.;Balasa, F.;Castro-Lopez, R.;Chang, Y.-W.;Fern;ez, F.V.;Lin, P.-H.;Strasser, M.; Graeb, H.; Balasa, F.; Castro-Lopez, R.; Chang, Y.-W.; Fern; ez, F.V.; Lin, P.-H.; Strasser, M.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:55Z	ILP-based pin-count aware design methodology for microfluidic biochips	Lin, C.C.-Y.;Chang, Y.-W.; Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:55Z	High-performance global routing with fast overflow reduction	YAO-WEN CHANG; Qien, H.-Y.;Hsu, C.-H.;Chang, Y.-W.; Qien, H.-Y.; Hsu, C.-H.; Chang, Y.-W.
臺大學術典藏	2018-09-10T07:36:55Z	Floorplanning	Chen, T.-C.;Chang, Y.-W.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:55Z	Essential issues in analytical placement algorithms	Chang, Y.-W.;Jiang, Z.-W.;Chen, T.-C.; Chang, Y.-W.; Jiang, Z.-W.; Chen, T.-C.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:54Z	Thermal-driven analog placement considering device matching	Lin, P.-H.;Zhang, H.;Wong, M.D.F.;Chang, Y.-W.; Lin, P.-H.; Zhang, H.; Wong, M.D.F.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:54Z	T-trees: A tree-based representation for temporal and three-dimensional floorplanning	Yuh, P.-H.;Yang, C.-L.;Chang, Y.-W.; Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; CHIA-LIN YANG
臺大學術典藏	2018-09-10T07:36:54Z	Spare-cell-aware multilevel analytical placement	Jiang, Z.-W.;Hsu, M.-K.;Chang, Y.-W.;Chao, K.-Y.; Jiang, Z.-W.; Hsu, M.-K.; Chang, Y.-W.; Chao, K.-Y.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:54Z	Simultaneous layout migration and decomposition for double patterning technology	Hsu, C.-H.;Chang, Y.-W.;Nassif, S.R.; Hsu, C.-H.; Chang, Y.-W.; Nassif, S.R.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:54Z	Routing for manufacturability and reliability	Chen, H.-Y.;Chang, Y.-W.; Chen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:54Z	Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs	Lee, W.-P.;Marculescu, D.;Chang, Y.-W.; Lee, W.-P.; Marculescu, D.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:54Z	Introduction	Stroud, C.E.;Wang, L.T.;Chang, Y.-W.; Stroud, C.E.; Wang, L.T.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:53Z	Voltage-island partitioning and floorplanning under timing constraints	Lee, W.-P.;Liu, H.-Y.;Chang, Y.-W.; Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:53Z	Voltage-Island partitioning and floorplanning under timing constraints	Lee, W.-P.;Liu, H.-Y.;Chang, Y.-W.; Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:36:53Z	Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs	Chuang, Y.-L.;Lee, P.-W.;Chang, Y.-W.; Chuang, Y.-L.; Lee, P.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏	2018-09-10T07:08:26Z	An Efficient Graph-Based Algorithm for ESD Current Path Analysis	C. H. Liu;H. Y. Liu;C. W. Lin;S. J. Chou;Y. W. Chang;S. Y. Kuo;S. Y. Yuan;Y. W. Chen; C. H. Liu; H. Y. Liu; C. W. Lin; S. J. Chou; Y. W. Chang; S. Y. Kuo; S. Y. Yuan; Y. W. Chen; SY-YEN KUO; YAO-WEN CHANG

Showing items 166-190 of 348 (14 Page(s) Totally)
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