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Taiwan Academic Institutional Repository >
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"yao wen chang"
Showing items 266-275 of 348 (35 Page(s) Totally)
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| 臺大學術典藏 |
2018-09-10T05:23:30Z |
A routing algorithm for flip-chip design
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Fang, J.-W.; Lin, I.-J.; Yuh, P.-H.; Chang, Y.-W.; Wang, J.-H.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:30Z |
FPGA global routing based on a new congestion metric
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Chang, Yao-Wen;Wong, D.F.;Wong, C.K.; Chang, Yao-Wen; Wong, D.F.; Wong, C.K.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:29Z |
Multilevel full-chip routing with testability and yield enhancement
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Li, K.S.-M.; Lee, C.-L.; Chang, Y.-W.; Su, C.; Chen, J.-E.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:29Z |
Multilevel full-chip routing for the X-based architecture
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Ho, T.-Y.; Chang, C.-F.; Chang, Y.-W.; Chen, S.-J.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:29Z |
Multilevel full-chip gridless routing considering optical proximity correction
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Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:29Z |
Modern floorplanning based on fast simulated annealing
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Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:28Z |
TCG: A transitive closure graph-based representation for general floorplans
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Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:28Z |
SoC test scheduling using the B*-tree based floorplanning technique
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Wuu, J.-Y.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:28Z |
Rlc coupling-Aware simulation for on-chip buses and their encoding for delay reduction
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Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:28Z |
Placement with symmetry constraints for analog layout design using TCG-S
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Lin, J.-M.; Wu, G.-M.; Chang, Y.-W.; Chuang, J.-H.; YAO-WEN CHANG |
Showing items 266-275 of 348 (35 Page(s) Totally)
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