| 臺大學術典藏 |
2018-09-10T04:33:03Z |
A Fast Crosstalk- and Performance-Driven Multilevel Routing System
|
Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Lee, D.T.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:33:02Z |
Rectilinear block placement using B*-trees
|
Wu, G.-M.; Chang, Y.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:33:02Z |
Noise-aware buffer planning for interconnect-driven floorplanning
|
Li, S.-M.; Cherng, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:33:02Z |
Multilevel floorplanning/placement for large-scale modules using B*-trees
|
YAO-WEN CHANG; Yang, H.H.; Hsu, J.-M.; Chang, Y.-W.; Lee, H.-C. |
| 臺大學術典藏 |
2018-09-10T04:33:02Z |
Graph matching-based algorithms for array-based FPGA segmentation design and routing
|
Lin, J.-M.; Pan, S.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:33:02Z |
Simultaneous floorplanning and buffer block planning
|
Hui-Ru Jiang, I.; Chang, Y.-W.; Jou, J.-Y.; Chao, K.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:54Z |
A novel framework for multilevel routing considering routability and performance
|
Lin, S.-P.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:53Z |
Module placement with boundary constraints using B*-trees
|
Lin, J.-M.; Yi, H.-E.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:53Z |
Inductance modeling for on-chip interconnects
|
Tu, S.-W.; Shen, W.-Z.; Chang, Y.-W.; Chen, T.-C.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:53Z |
Formulae for performance optimization and their applications to interconnect-driven floorplanning
|
Chang, N.C.-Y.; Chang, Y.-W.; Jian, I.H.-R.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:53Z |
Comment on "generic universal switch blocks"
|
Fan, H.; Wu, Y.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:53Z |
Arbitrary convex and concave rectilinear module packing using TCG
|
Lin, J.-M.; Chen, H.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:53Z |
Arbitrarily shaped rectilinear module placement using the transitive closure graph representation
|
Lin, J.-M.; Chen, H.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:52Z |
Performance-driven placement for dynamically reconfigurable FPGAs
|
Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; Wu, Guang-Ming; Lin, Jai-Ming; Chang, Yao-Wen; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T03:47:58Z |
Generic ILP-based approaches for time-multiplexed FPGA partitioning
|
Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T03:47:57Z |
Performance optimization by wire and buffer sizing under the transmission line model
|
Chen, T.-C.; Pan, S.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T03:29:38Z |
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
|
Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T03:29:38Z |
Crosstalk-constrained performance optimization by using wire sizing and perturbation
|
Pan, Song-Ra; Chang, Yao-Wen; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T03:29:38Z |
B*-trees: a new representation for non-slicing floorplans
|
Chang, Yun-Chih; Chang, Yao-Wen; Wu, Guang-Ming; Wu, Shu-Wei; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T03:29:38Z |
Architecture-driven metric for simultaneous placement and global routing for FPGAs
|
YAO-WEN CHANG; Chang, Yu-Tsang; Chang, Yao-Wen |
| 臺大學術典藏 |
2018-09-10T03:29:37Z |
Timing-driven routing for symmetrical array-based FPGAs
|
Chang, Y.-W.; Zhu, K.; Wong, D.F.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T03:29:37Z |
Rectilinear block placement using B*-trees
|
Wu, Guang-Ming; Chang, Yun-Chih; Chang, Yao-Wen; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T03:29:37Z |
Optimal reliable crosstalk-driven interconnect optimization
|
Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; Jou, Jing-Yang; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T03:29:37Z |
Generic universal switch blocks
|
Shyu, M.; Wu, G.-M.; Chang, Y.-D.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T03:29:37Z |
Crosstalkdriven interconnect optimization by simultaneous gate and wire sizing
|
Jiang, I.H.R.; Chang, Y.W.; Jou, J.Y.; YAO-WEN CHANG |
