| 臺大學術典藏 |
2018-09-10T04:53:44Z |
RLC effects on worst-case switching pattern for on-chip buses
|
Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Universal switch blocks for three-dimensional FPGA design
|
Wu, G.-M.; Shyu, M.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Temporal floorplanning using the T-tree formulation
|
Yuh, P.-H.;Yang, C.-L.;Chang, Y.-W.; Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Temporal floorplanning using 3D-subTCG
|
Yuh, P.-H.;Yang, C.-L.;Chang, Y.-W.;Chen, H.-L.; Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; Chen, H.-L.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
TCG-S: Orthogonal coupling of P*-admissible representations for general floorplans
|
Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Placement with alignment and performance constraints using the B*-tree representation
|
Wu, M.-C.; Chang, Y.-W.; Wu, M.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Multilevel routing with jumper insertion for antenna avoidance
|
Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Multilevel routing with antenna avoidance
|
Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Layout techniques for on-chip interconnect inductance reduction
|
Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:33:03Z |
Switch module design with application to two-dimensional segmentation design
|
Zhu, Kai; Wong, D.F.; Chang, Yao-Wen; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:33:03Z |
A Fast Crosstalk- and Performance-Driven Multilevel Routing System
|
Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Lee, D.T.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:33:02Z |
Rectilinear block placement using B*-trees
|
Wu, G.-M.; Chang, Y.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:33:02Z |
Noise-aware buffer planning for interconnect-driven floorplanning
|
Li, S.-M.; Cherng, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:33:02Z |
Multilevel floorplanning/placement for large-scale modules using B*-trees
|
YAO-WEN CHANG; Yang, H.H.; Hsu, J.-M.; Chang, Y.-W.; Lee, H.-C. |
| 臺大學術典藏 |
2018-09-10T04:33:02Z |
Graph matching-based algorithms for array-based FPGA segmentation design and routing
|
Lin, J.-M.; Pan, S.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:33:02Z |
Simultaneous floorplanning and buffer block planning
|
Hui-Ru Jiang, I.; Chang, Y.-W.; Jou, J.-Y.; Chao, K.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:54Z |
A novel framework for multilevel routing considering routability and performance
|
Lin, S.-P.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:53Z |
Module placement with boundary constraints using B*-trees
|
Lin, J.-M.; Yi, H.-E.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:53Z |
Inductance modeling for on-chip interconnects
|
Tu, S.-W.; Shen, W.-Z.; Chang, Y.-W.; Chen, T.-C.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:53Z |
Formulae for performance optimization and their applications to interconnect-driven floorplanning
|
Chang, N.C.-Y.; Chang, Y.-W.; Jian, I.H.-R.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:53Z |
Comment on "generic universal switch blocks"
|
Fan, H.; Wu, Y.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:53Z |
Arbitrary convex and concave rectilinear module packing using TCG
|
Lin, J.-M.; Chen, H.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:53Z |
Arbitrarily shaped rectilinear module placement using the transitive closure graph representation
|
Lin, J.-M.; Chen, H.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:52Z |
Performance-driven placement for dynamically reconfigurable FPGAs
|
Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; Wu, Guang-Ming; Lin, Jai-Ming; Chang, Yao-Wen; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T03:47:58Z |
Generic ILP-based approaches for time-multiplexed FPGA partitioning
|
Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG |
