| 臺大學術典藏 |
2022-04-25T06:44:15Z |
A Bridge-based Compression Algorithm for Topological Quantum Circuits
|
Hsu C.-H;Lin W.-H;Tseng W.-H;Chang Y.-W.; Hsu C.-H; Lin W.-H; Tseng W.-H; Chang Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2022-04-25T06:44:14Z |
Simultaneous Pre-and Free-assignment Routing for Multiple Redistribution Layers with Irregular Vias
|
Cai Y.-J;Hsu Y;Chang Y.-W.; Cai Y.-J; Hsu Y; Chang Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2022-04-14T23:28:00Z |
On-chip Optical Routing with Waveguide Matching Constraints
|
Chuang, Fu Yu; YAO-WEN CHANG |
| 臺大學術典藏 |
2022-02-14T23:56:18Z |
A Row-Based Algorithm for Non-Integer Multiple-Cell-Height Placement
|
Lin, Zih Yao; YAO-WEN CHANG |
| 臺大學術典藏 |
2022-02-14T23:56:18Z |
Time-Division Multiplexing Based System-Level FPGA Routing
|
Liu, Wei Kai; Chen, Ming Hung; CHIA-MING CHANG; Chang, Chen Chia; YAO-WEN CHANG |
| 臺大學術典藏 |
2022-01-15T00:08:41Z |
Timing-Aware Fill Insertions with Design-Rule and Density Constraints
|
Bai, Xiqiong; Zhu, Ziran; Li, Pingping; Chen, Jianli; Lan, Tingshen; Li, Xingquan; Yu, Jun; Zhu, Wenxing; YAO-WEN CHANG |
| 臺大學術典藏 |
2022-01-15T00:08:40Z |
On-Chip Optical Routing with Provably Good Algorithms for Path Clustering and Assignment
|
Lu, Yu Sheng; Yu, Sheng Jung; YAO-WEN CHANG |
| 臺大學術典藏 |
2021-12-14T23:12:45Z |
Simultaneous Pre-and Free-assignment Routing for Multiple Redistribution Layers with Irregular Vias
|
Cai, Yu Jie; Hsu, Yang; YAO-WEN CHANG |
| 臺大學術典藏 |
2021-12-14T23:12:45Z |
VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units
|
Chou, Yun; Hsu, Jhih Wei; YAO-WEN CHANG; Chen, Tung Chieh |
| 臺大學術典藏 |
2021-12-14T23:12:45Z |
Two-Stage Neural Network Classifier for the Data Imbalance Problem with Application to Hotspot Detection
|
Wang, Bingshu; Jiang, Lanfan; Zhu, Wenxing; Guo, Longkun; Chen, Jianli; YAO-WEN CHANG |
| 臺大學術典藏 |
2021-12-14T23:12:45Z |
Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA Systems
|
Chen, Ming Hung; YAO-WEN CHANG; Wang, Jun Jie |
| 臺大學術典藏 |
2021-12-14T23:12:45Z |
A Bridge-based Compression Algorithm for Topological Quantum Circuits
|
Hsu, Chen Hao; Lin, Wan Hsuan; Tseng, Wei Hsiang; YAO-WEN CHANG |
| 臺大學術典藏 |
2021-09-14T23:19:25Z |
Topological Structure and Physical Layout Co-design for Wavelength-Routed Optical Networks-on-Chip
|
Lu, Yu Sheng; Chen, Yan Lin; Yu, Sheng Jung; YAO-WEN CHANG |
| 臺大學術典藏 |
2021-09-02T00:09:08Z |
Analytical Placement Considering the Electron-Beam Fogging Effect
|
Chen J;Chang Y.-W;Huang Y.-C.; Chen J; Chang Y.-W; Huang Y.-C.; YAO-WEN CHANG |
| 臺大學術典藏 |
2021-09-02T00:09:08Z |
A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing
|
Hsu C.-H;Hung S.-C;Chen H;Sun F.-K;Chang Y.-W.; Hsu C.-H; Hung S.-C; Chen H; Sun F.-K; Chang Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2021-09-02T00:09:07Z |
Analytical placement with 3D poisson's equation and ADMM based optimization for large-scale 2.5D heterogeneous FPGAs
|
Chen J;Zhu W;Yu J;He L;Chang Y.-W.; Chen J; Zhu W; Yu J; He L; Chang Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2021-09-02T00:09:07Z |
Mixed-Cell-Height Legalization Considering Technology and Region Constraints
|
Zhu Z;Chen J;Zhu W;Chang Y.-W.; Zhu Z; Chen J; Zhu W; Chang Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2021-09-02T00:09:07Z |
Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration
|
Jiang I.H.-R;Chang Y.-W;Huang J.-L;Chen C.-P.; Jiang I.H.-R; Chang Y.-W; Huang J.-L; Chen C.-P.; YAO-WEN CHANG |
| 臺大學術典藏 |
2021-09-02T00:09:07Z |
Clock-Aware Placement for Large-Scale Heterogeneous FPGAs
|
Chen J;Lin Z;Kuo Y.-C;Huang C.-C;Chang Y.-W;Chen S.-C;Chiang C.-H;Kuo S.-Y.; Chen J; Lin Z; Kuo Y.-C; Huang C.-C; Chang Y.-W; Chen S.-C; Chiang C.-H; Kuo S.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2021-09-02T00:09:06Z |
Opportunities for 2.5/3D Heterogeneous SoC Integration
|
Jiang I.H.-R;Chang Y.-W;Huang J.-L;Chen C.-P.; Jiang I.H.-R; Chang Y.-W; Huang J.-L; Chen C.-P.; YAO-WEN CHANG |
| 臺大學術典藏 |
2021-09-02T00:09:06Z |
Mixed-Cell-Height Placement with Drain-to-Drain Abutment and Region Constraints
|
Chen J;Zhu Z;Guo L;Tseng Y;Chang Y.; Chen J; Zhu Z; Guo L; Tseng Y; Chang Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2021-09-02T00:09:06Z |
Timing-aware fill insertions with design-rule and density constraints
|
Lan T;Li X;Chen J;Yu J;He L;Dong S;Zhu W;Chang Y.-W.; Lan T; Li X; Chen J; Yu J; He L; Dong S; Zhu W; Chang Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2021-09-02T00:09:06Z |
Routability-Aware Pin Access Optimization for Monolithic 3D Designs*
|
Wang R.-Y;Chang Y.-W.; Wang R.-Y; Chang Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2021-07-15T05:32:57Z |
Opportunities for 2.5/3D Heterogeneous SoC Integration
|
HUI-RU JIANG; YAO-WEN CHANG; JIUN-LANG HUANG; CHUNG-PING CHEN |
| 臺大學術典藏 |
2021-07-15T05:32:57Z |
Mixed-Cell-Height Placement with Drain-to-Drain Abutment and Region Constraints
|
Chen, Jianli; Zhu, Ziran; Guo, Longkun; Tseng, Yu Wei; YAO-WEN CHANG |
