| 臺大學術典藏 |
2018-09-10T09:48:07Z |
Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling
|
Fang, S.-Y.;Lin, C.-W.;Liao, G.-W.;Chang, Y.-W.; Fang, S.-Y.; Lin, C.-W.; Liao, G.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:48:07Z |
Simultaneous analog placement and routing with current flow and current density considerations
|
Ou, H.-C.;Chien, H.-C.C.;Chang, Y.-W.; Ou, H.-C.; Chien, H.-C.C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:48:07Z |
Routability-driven placement for hierarchical mixed-size circuit designs
|
Hsu, M.-K.;Chen, Y.-F.;Huang, C.-C.;Chen, T.-C.;Chang, Y.-W.; Hsu, M.-K.; Chen, Y.-F.; Huang, C.-C.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:48:07Z |
Multiple chip planning for chip-interposer codesign
|
Ho, Y.-K.;Chang, Y.-W.; Ho, Y.-K.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:48:07Z |
Graph-based subfield scheduling for electron-beam photomask fabrication
|
Fang, S.-Y.;Chen, W.-Y.;Chang, Y.-W.; Fang, S.-Y.; Chen, W.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:24:00Z |
Correlation effects of π electrons on the band structures of conjugated polymers using the self-consistent GW approximation with vertex corrections
|
Yao-Wen Chang; Bih-Yaw Jin; Yao-Wen Chang; Bih-Yaw Jin; BIH-YAW JIN |
| 臺大學術典藏 |
2018-09-10T09:22:26Z |
Non-uniform multilevel analog routing with matching constraints
|
Ou, H.-C.; Chien, H.-C.C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:26Z |
Native-conflict and stitch-aware wire perturbation for double patterning technology
|
Fang, S.-Y.; Chen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:26Z |
Graph-based subfield scheduling for electron-beam photomask fabrication
|
Fang, S.-Y.; Chen, W.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:26Z |
Fast timing-model independent buffered clock-tree synthesis
|
Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:26Z |
An efficient Pre-assignment routing algorithm for flip-chip designs
|
Lin, C.-W.; Lee, P.-W.; Chang, Y.-W.; Shen, C.-F.; Tseng, W.-C.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:26Z |
A novel layout decomposition algorithm for triple patterning lithography
|
Fang, S.-Y.; Chang, Y.-W.; Chen, W.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:26Z |
A chip-package-board co-design methodology
|
Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Unified analytical global placement for large-scale mixed-size circuit designs
|
Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
TRECO: Dynamic technology remapping for timing engineering change orders
|
Ho, K.-H.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Timing ECO optimization via B?zier curve smoothing and fixability identification
|
Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Timing ECO optimization using metal-configurable gate-array spare cells
|
Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Structure-aware placement for datapath-intensive circuit designs
|
Chou, S.; Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Simultaneous flare level and flare variation minimization with dummification in EUVL
|
Fang, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Obstacle-avoiding free-assignment routing for flip-chip designs
|
Lee, P.-W.; Lee, H.-C.; Ho, Y.-K.; Chang, Y.-W.; Chang, C.-F.; Lin, I.-J.; Shen, C.-F.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:39Z |
A corner stitching compliant B-tree representation and its applications to analog placement
|
YAO-WEN CHANG; Tsao, H.-F.;Chou, P.-Y.;Huang, S.-L.;Chang, Y.-W.;Lin, M.P.-H.;Chen, D.-P.;Liu, D.; Tsao, H.-F.; Chou, P.-Y.; Huang, S.-L.; Chang, Y.-W.; Lin, M.P.-H.; Chen, D.-P.; Liu, D. |
| 臺大學術典藏 |
2018-09-10T08:42:38Z |
Hierarchical placement with layout constraints
|
Lin, M.P.-H.;Chang, Y.-W.; Lin, M.P.-H.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:38Z |
Heterogeneous B*-trees for analog placement with symmetry and regularity considerations
|
Chou, P.-Y.;Ou, H.-C.;Chang, Y.-W.; Chou, P.-Y.; Ou, H.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:38Z |
Escape routing for staggered-pin-array PCBs
|
Ho, Y.-K.;Lee, H.-C.;Chang, Y.-W.; Ho, Y.-K.; Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:38Z |
Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips
|
Lin, C.C.-Y.;Chang, Y.-W.; Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
