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"yao wen chang"的相關文件
顯示項目 111-135 / 348 (共14頁)
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| 臺大學術典藏 |
2018-09-10T09:24:00Z |
Correlation effects of π electrons on the band structures of conjugated polymers using the self-consistent GW approximation with vertex corrections
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Yao-Wen Chang; Bih-Yaw Jin; Yao-Wen Chang; Bih-Yaw Jin; BIH-YAW JIN |
| 臺大學術典藏 |
2018-09-10T09:22:26Z |
Non-uniform multilevel analog routing with matching constraints
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Ou, H.-C.; Chien, H.-C.C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:26Z |
Native-conflict and stitch-aware wire perturbation for double patterning technology
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Fang, S.-Y.; Chen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:26Z |
Graph-based subfield scheduling for electron-beam photomask fabrication
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Fang, S.-Y.; Chen, W.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:26Z |
Fast timing-model independent buffered clock-tree synthesis
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Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:26Z |
An efficient Pre-assignment routing algorithm for flip-chip designs
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Lin, C.-W.; Lee, P.-W.; Chang, Y.-W.; Shen, C.-F.; Tseng, W.-C.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:26Z |
A novel layout decomposition algorithm for triple patterning lithography
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Fang, S.-Y.; Chang, Y.-W.; Chen, W.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:26Z |
A chip-package-board co-design methodology
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Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Unified analytical global placement for large-scale mixed-size circuit designs
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Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
TRECO: Dynamic technology remapping for timing engineering change orders
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Ho, K.-H.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Timing ECO optimization via B?zier curve smoothing and fixability identification
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Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Timing ECO optimization using metal-configurable gate-array spare cells
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Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Structure-aware placement for datapath-intensive circuit designs
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Chou, S.; Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Simultaneous flare level and flare variation minimization with dummification in EUVL
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Fang, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Obstacle-avoiding free-assignment routing for flip-chip designs
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Lee, P.-W.; Lee, H.-C.; Ho, Y.-K.; Chang, Y.-W.; Chang, C.-F.; Lin, I.-J.; Shen, C.-F.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:39Z |
A corner stitching compliant B-tree representation and its applications to analog placement
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YAO-WEN CHANG; Tsao, H.-F.;Chou, P.-Y.;Huang, S.-L.;Chang, Y.-W.;Lin, M.P.-H.;Chen, D.-P.;Liu, D.; Tsao, H.-F.; Chou, P.-Y.; Huang, S.-L.; Chang, Y.-W.; Lin, M.P.-H.; Chen, D.-P.; Liu, D. |
| 臺大學術典藏 |
2018-09-10T08:42:38Z |
Hierarchical placement with layout constraints
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Lin, M.P.-H.;Chang, Y.-W.; Lin, M.P.-H.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:38Z |
Heterogeneous B*-trees for analog placement with symmetry and regularity considerations
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Chou, P.-Y.;Ou, H.-C.;Chang, Y.-W.; Chou, P.-Y.; Ou, H.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:38Z |
Escape routing for staggered-pin-array PCBs
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Ho, Y.-K.;Lee, H.-C.;Chang, Y.-W.; Ho, Y.-K.; Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:38Z |
Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips
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Lin, C.C.-Y.;Chang, Y.-W.; Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:38Z |
An EOS-Free PNP-enhanced cascoded NMOSFET structure for high voltage application
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Wang, S.-Y.;Chang, Y.-W.;Chen, Y.-Y.;He, C.-W.;Wu, G.-W.;Lu, T.-C.;Chen, K.-C.;Lu, C.-Y.; Wang, S.-Y.; Chang, Y.-W.; Chen, Y.-Y.; He, C.-W.; Wu, G.-W.; Lu, T.-C.; Chen, K.-C.; Lu, C.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:37Z |
Simultaneous functional and timing ECO
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Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:37Z |
Routability-driven analytical placement for mixed-size circuit designs
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Hsu, M.-K.;Chou, S.;Lin, T.-H.;Chang, Y.-W.; Hsu, M.-K.; Chou, S.; Lin, T.-H.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:37Z |
Pulsed-latch aware placement for timing-integrity optimization
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Chuang, Y.-L.;Kim, S.;Shin, Y.;Chang, Y.-W.; Chuang, Y.-L.; Kim, S.; Shin, Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:37Z |
Proceedings of the International Symposium on Physical Design: Foreword
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Chang, Y.-W.;Hu, J.; Chang, Y.-W.; Hu, J.; YAO-WEN CHANG |
顯示項目 111-135 / 348 (共14頁)
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