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"yao wen chang"的相关文件
显示项目 116-125 / 348 (共35页)
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每页显示[10|25|50]项目
| 臺大學術典藏 |
2018-09-10T09:22:26Z |
An efficient Pre-assignment routing algorithm for flip-chip designs
|
Lin, C.-W.; Lee, P.-W.; Chang, Y.-W.; Shen, C.-F.; Tseng, W.-C.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:26Z |
A novel layout decomposition algorithm for triple patterning lithography
|
Fang, S.-Y.; Chang, Y.-W.; Chen, W.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:26Z |
A chip-package-board co-design methodology
|
Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Unified analytical global placement for large-scale mixed-size circuit designs
|
Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
TRECO: Dynamic technology remapping for timing engineering change orders
|
Ho, K.-H.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Timing ECO optimization via B?zier curve smoothing and fixability identification
|
Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Timing ECO optimization using metal-configurable gate-array spare cells
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Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Structure-aware placement for datapath-intensive circuit designs
|
Chou, S.; Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Simultaneous flare level and flare variation minimization with dummification in EUVL
|
Fang, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Obstacle-avoiding free-assignment routing for flip-chip designs
|
Lee, P.-W.; Lee, H.-C.; Ho, Y.-K.; Chang, Y.-W.; Chang, C.-F.; Lin, I.-J.; Shen, C.-F.; YAO-WEN CHANG |
显示项目 116-125 / 348 (共35页)
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