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"yao wen chang"的相关文件
显示项目 121-130 / 348 (共35页)
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| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Timing ECO optimization via B?zier curve smoothing and fixability identification
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Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Timing ECO optimization using metal-configurable gate-array spare cells
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Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Structure-aware placement for datapath-intensive circuit designs
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Chou, S.; Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Simultaneous flare level and flare variation minimization with dummification in EUVL
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Fang, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
Obstacle-avoiding free-assignment routing for flip-chip designs
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Lee, P.-W.; Lee, H.-C.; Ho, Y.-K.; Chang, Y.-W.; Chang, C.-F.; Lin, I.-J.; Shen, C.-F.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:39Z |
A corner stitching compliant B-tree representation and its applications to analog placement
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YAO-WEN CHANG; Tsao, H.-F.;Chou, P.-Y.;Huang, S.-L.;Chang, Y.-W.;Lin, M.P.-H.;Chen, D.-P.;Liu, D.; Tsao, H.-F.; Chou, P.-Y.; Huang, S.-L.; Chang, Y.-W.; Lin, M.P.-H.; Chen, D.-P.; Liu, D. |
| 臺大學術典藏 |
2018-09-10T08:42:38Z |
Hierarchical placement with layout constraints
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Lin, M.P.-H.;Chang, Y.-W.; Lin, M.P.-H.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:38Z |
Heterogeneous B*-trees for analog placement with symmetry and regularity considerations
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Chou, P.-Y.;Ou, H.-C.;Chang, Y.-W.; Chou, P.-Y.; Ou, H.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:38Z |
Escape routing for staggered-pin-array PCBs
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Ho, Y.-K.;Lee, H.-C.;Chang, Y.-W.; Ho, Y.-K.; Lee, H.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:38Z |
Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips
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Lin, C.C.-Y.;Chang, Y.-W.; Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
显示项目 121-130 / 348 (共35页)
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