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"yao wen chang"的相關文件
顯示項目 136-160 / 348 (共14頁)
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| 臺大學術典藏 |
2018-09-10T08:42:37Z |
PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs
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Chuang, Y.-L.;Lin, H.-T.;Ho, T.-Y.;Chang, Y.-W.;Marculescu, D.; Chuang, Y.-L.; Lin, H.-T.; Ho, T.-Y.; Chang, Y.-W.; Marculescu, D.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:37Z |
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems: Guest Editorial
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Saxena, P.;Chang, Y.-W.; Saxena, P.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:36Z |
Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs
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Chuang, Y.-L.;Lee, P.-W.;Chang, Y.-W.; Chuang, Y.-L.; Lee, P.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:36Z |
TSV-aware analytical placement for 3D IC designs
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Hsu, M.-K.;Chang, Y.-W.;Balabanov, V.; Hsu, M.-K.; Chang, Y.-W.; Balabanov, V.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:36Z |
Timing ECO optimization via B?zier curve smoothing and fixability identification
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Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:42:36Z |
Thermal-driven analog placement considering device matching
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YAO-WEN CHANG; Chang, Y.-W.; Wong, M.D.F.; Lin, M.P.-H.; Zhang, H.; Lin, M.P.-H.;Zhang, H.;Wong, M.D.F.;Chang, Y.-W. |
| 臺大學術典藏 |
2018-09-10T08:42:36Z |
Simultaneous layout migration and decomposition for double patterning technology
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Hsu, C.-H.;Chang, Y.-W.;Nassif, S.R.; Hsu, C.-H.; Chang, Y.-W.; Nassif, S.R.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:39:31Z |
A SAT-based routing algorithm for cross-referencing biochips
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Yuh, P.-H.;Lin, C.C.-Y.;Huang, T.-W.;Ho, T.-Y.;Yang, C.-L.;Chang, Y.-W.; Yuh, P.-H.; Lin, C.C.-Y.; Huang, T.-W.; Ho, T.-Y.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T08:19:13Z |
TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders
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Kuan-Hsien Ho;Jie-Hong R. Jiang;Yao-Wen Chang; Kuan-Hsien Ho; Jie-Hong R. Jiang; Yao-Wen Chang; YAO-WEN CHANG; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T08:17:03Z |
Effect of Broken Symmetry on the First Hyperpolarizability of a Centrosymmetric Molecule with an Application to Furan-Containing [2.2]Cyclophandiene
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Yao-Wen Chang;Bih-Yaw Jin; Yao-Wen Chang; Bih-Yaw Jin; Chang, Yao-Wen; BIH-YAW JIN |
| 臺大學術典藏 |
2018-09-10T08:14:58Z |
ECO timing optimization using spare cells and technology remapping
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Ho, K.-H.; Chen, Y.-P.; Fang, J.-W.; Chang, Y.-W.; Ho, K.-H.; Chen, Y.-P.; Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:58Z |
Design-hierarchy aware mixed-size placement for routability optimization
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Chuang, Y.-L.; Nam, G.-J.; Alpert, C.J.; Chang, Y.-W.; Roy, J.; Viswanathan, N.; Chuang, Y.-L.; Nam, G.-J.; Alpert, C.J.; Chang, Y.-W.; Roy, J.; Viswanathan, N.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:58Z |
Density gradient minimization with coupling-constrained dummy fill for CMP control
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Chen, H.-Y.; Chou, S.-J.; Chang, Y.-W.; Chen, H.-Y.; Chou, S.-J.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:58Z |
Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips
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Lin, C.C.-Y.; Chang, Y.-W.; Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:58Z |
Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization
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Shih, X.-W.; Cheng, C.-C.; Ho, Y.-K.; Chang, Y.-W.; Shih, X.-W.; Cheng, C.-C.; Ho, Y.-K.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:58Z |
Area-I/O flip-chip routing for chip-package co-design considering signal skews
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Fang, J.-W.; Chang, Y.-W.; Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:57Z |
Predictive formulae for OPC with applications to lithography-friendly routing
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Chen, T.-C.; Liao, G.-W.; Chang, Y.-W.; Chen, T.-C.; Liao, G.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:57Z |
Native-conflict-aware wire perturbation for double patterning technology
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Chen, S.-Y.;Chang, Y.-W.; Chen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:57Z |
Multilayer global routing with via and wire capacity considerations
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Hsu, C.-H.; Chen, H.-Y.; Chang, Y.-W.; Hsu, C.-H.; Chen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:57Z |
ILP-based pin-count aware design methodology for microfluidic biochips
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Lin, C.C.-Y.; Chang, Y.-W.; Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:57Z |
High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees
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Shiht, X.-W.; Leet, H.-C.; Hot, K.-H.; Chang, Y.-W.; Shiht, X.-W.; Leet, H.-C.; Hot, K.-H.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:57Z |
Fast timing-model independent buffered clock-tree synthesis
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Shih, X.-W.; Chang, Y.-W.; Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:57Z |
Efficient provably good OPC modeling and its applications to interconnect optimization
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Huang, S.-L.; Lin, C.-W.; Chang, Y.-W.; Huang, S.-L.; Lin, C.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:56Z |
Unified analytical global placement for large-scale mixed-size circuit designs
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Hsu, M.-K.;Chang, Y.-W.; Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:56Z |
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis
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Falkenstern, P.; Xie, Y.; Chang, Y.-W.; Wang, Y.; YAO-WEN CHANG; Falkenstern, P.;Xie, Y.;Chang, Y.-W.;Wang, Y. |
顯示項目 136-160 / 348 (共14頁)
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