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Showing items 146-170 of 348 (14 Page(s) Totally)
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| 臺大學術典藏 |
2018-09-10T08:14:58Z |
ECO timing optimization using spare cells and technology remapping
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Ho, K.-H.; Chen, Y.-P.; Fang, J.-W.; Chang, Y.-W.; Ho, K.-H.; Chen, Y.-P.; Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:58Z |
Design-hierarchy aware mixed-size placement for routability optimization
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Chuang, Y.-L.; Nam, G.-J.; Alpert, C.J.; Chang, Y.-W.; Roy, J.; Viswanathan, N.; Chuang, Y.-L.; Nam, G.-J.; Alpert, C.J.; Chang, Y.-W.; Roy, J.; Viswanathan, N.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:58Z |
Density gradient minimization with coupling-constrained dummy fill for CMP control
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Chen, H.-Y.; Chou, S.-J.; Chang, Y.-W.; Chen, H.-Y.; Chou, S.-J.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:58Z |
Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips
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Lin, C.C.-Y.; Chang, Y.-W.; Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:58Z |
Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization
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Shih, X.-W.; Cheng, C.-C.; Ho, Y.-K.; Chang, Y.-W.; Shih, X.-W.; Cheng, C.-C.; Ho, Y.-K.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:58Z |
Area-I/O flip-chip routing for chip-package co-design considering signal skews
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Fang, J.-W.; Chang, Y.-W.; Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:57Z |
Predictive formulae for OPC with applications to lithography-friendly routing
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Chen, T.-C.; Liao, G.-W.; Chang, Y.-W.; Chen, T.-C.; Liao, G.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:57Z |
Native-conflict-aware wire perturbation for double patterning technology
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Chen, S.-Y.;Chang, Y.-W.; Chen, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:57Z |
Multilayer global routing with via and wire capacity considerations
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Hsu, C.-H.; Chen, H.-Y.; Chang, Y.-W.; Hsu, C.-H.; Chen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:57Z |
ILP-based pin-count aware design methodology for microfluidic biochips
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Lin, C.C.-Y.; Chang, Y.-W.; Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:57Z |
High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees
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Shiht, X.-W.; Leet, H.-C.; Hot, K.-H.; Chang, Y.-W.; Shiht, X.-W.; Leet, H.-C.; Hot, K.-H.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:57Z |
Fast timing-model independent buffered clock-tree synthesis
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Shih, X.-W.; Chang, Y.-W.; Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:57Z |
Efficient provably good OPC modeling and its applications to interconnect optimization
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Huang, S.-L.; Lin, C.-W.; Chang, Y.-W.; Huang, S.-L.; Lin, C.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:56Z |
Unified analytical global placement for large-scale mixed-size circuit designs
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Hsu, M.-K.;Chang, Y.-W.; Hsu, M.-K.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:56Z |
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis
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Falkenstern, P.; Xie, Y.; Chang, Y.-W.; Wang, Y.; YAO-WEN CHANG; Falkenstern, P.;Xie, Y.;Chang, Y.-W.;Wang, Y. |
| 臺大學術典藏 |
2018-09-10T08:14:56Z |
Template-mask design methodology for double patterning technology
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Hsu, C.-H.;Chang, Y.-W.;Nassif, S.R.; Hsu, C.-H.; Chang, Y.-W.; Nassif, S.R.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:56Z |
Redundant-wires-aware ECO timing and mask cost optimization
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Fang, S.-Y.; Chien, T.-F.; Chang, Y.-W.; Fang, S.-Y.; Chien, T.-F.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T08:14:56Z |
Pulsed-latch aware placement for timing-integrity optimization
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Chuang, Y.-L.; Kim, S.; Shin, Y.; Chang, Y.-W.; Chuang, Y.-L.; Kim, S.; Shin, Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:58Z |
Generic universal switch blocks
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Shyu, Michael; Chang, Yu-Dong; Wu, Guang-Ming; Chang, Yao-Wen; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:58Z |
Clustering- and probability-based approach for time-multiplexed FPGA partitioning
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Chang, Yao-Wen; YAO-WEN CHANG; Jiang, Iris Hui-Ru; Chao, Mango Chia-Tso; Wu, Guang-Ming |
| 臺大學術典藏 |
2018-09-10T07:36:57Z |
An efficient pre-assignment routing algorithm for flip-chip designs
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Lee, P.-W.;Lin, C.-W.;Chang, Y.-W.;Shen, C.-F.;Tseng, W.-C.; Lee, P.-W.; Lin, C.-W.; Chang, Y.-W.; Shen, C.-F.; Tseng, W.-C.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:57Z |
A progressive-ILP-based routing algorithm for the synthesis of cross-referencing biochips
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Yuh, P.-H.;Sapatnekar, S.S.;Yang, C.-L.;Chang, Y.-W.; Yuh, P.-H.; Sapatnekar, S.S.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T07:36:57Z |
A novel wire-density-driven full-chip routing system for cmp variation control
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Chen, H.-Y.;Chou, S.-J.;Wang, S.-L.;Chang, Y.-W.; Chen, H.-Y.; Chou, S.-J.; Wang, S.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:57Z |
A novel wire-density-driven full-chip routing system for CMP variation control
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Chen, H.-Y.;Chou, S.-J.;Wang, S.-L.;Chang, Y.-W.; Chen, H.-Y.; Chou, S.-J.; Wang, S.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:57Z |
A novel hot-electron programming method in a buried diffusion bit-line SONOS memory by utilizing nonequilibrium charge transport
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Wang, T.;Tang, C.-J.;Li, C.-W.;Lee, C.-H.;Ou, T.-F.;Chang, Y.-W.;Tsai, W.-J.;Lu, T.-C.;Chen, K.-C.;Lu, C.-Y.; Wang, T.; Tang, C.-J.; Li, C.-W.; Lee, C.-H.; Ou, T.-F.; Chang, Y.-W.; Tsai, W.-J.; Lu, T.-C.; Chen, K.-C.; Lu, C.-Y.; YAO-WEN CHANG |
Showing items 146-170 of 348 (14 Page(s) Totally)
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