| 臺大學術典藏 |
2018-09-10T07:36:57Z |
Quasi-universal switch matrices for FPD design
|
Wu, G.-M.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:56Z |
BIST design optimization for large-scale embedded memory cores
|
Chien, T.-F.;Chao, W.-C.;Li, C.-M.;Chang, Y.-W.;Liao, K.-Y.;Chang, M.-T.;Tsai, M.-H.;Tseng, C.-M.; Chien, T.-F.; Chao, W.-C.; Li, C.-M.; Chang, Y.-W.; Liao, K.-Y.; Chang, M.-T.; Tsai, M.-H.; Tseng, C.-M.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:56Z |
Analog placement based on symmetry-island formulation
|
Lin, P.-H.;Chang, Y.-W.;Lin, S.-C.; Lin, P.-H.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:56Z |
Analog placement based on symmetry-Island formulation
|
Lin, P.-H.;Chang, Y.-W.;Lin, S.-C.; Lin, P.-H.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:56Z |
Analog layout synthesis - Recent advances in topological approaches
|
Graeb, H.;Balasa, F.;Castro-Lopez, R.;Chang, Y.-W.;Fern;ez, F.V.;Lin, P.-H.;Strasser, M.; Graeb, H.; Balasa, F.; Castro-Lopez, R.; Chang, Y.-W.; Fern; ez, F.V.; Lin, P.-H.; Strasser, M.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:55Z |
ILP-based pin-count aware design methodology for microfluidic biochips
|
Lin, C.C.-Y.;Chang, Y.-W.; Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:55Z |
High-performance global routing with fast overflow reduction
|
YAO-WEN CHANG; Qien, H.-Y.;Hsu, C.-H.;Chang, Y.-W.; Qien, H.-Y.; Hsu, C.-H.; Chang, Y.-W. |
| 臺大學術典藏 |
2018-09-10T07:36:55Z |
Floorplanning
|
Chen, T.-C.;Chang, Y.-W.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:55Z |
Essential issues in analytical placement algorithms
|
Chang, Y.-W.;Jiang, Z.-W.;Chen, T.-C.; Chang, Y.-W.; Jiang, Z.-W.; Chen, T.-C.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:54Z |
Thermal-driven analog placement considering device matching
|
Lin, P.-H.;Zhang, H.;Wong, M.D.F.;Chang, Y.-W.; Lin, P.-H.; Zhang, H.; Wong, M.D.F.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:54Z |
T-trees: A tree-based representation for temporal and three-dimensional floorplanning
|
Yuh, P.-H.;Yang, C.-L.;Chang, Y.-W.; Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T07:36:54Z |
Spare-cell-aware multilevel analytical placement
|
Jiang, Z.-W.;Hsu, M.-K.;Chang, Y.-W.;Chao, K.-Y.; Jiang, Z.-W.; Hsu, M.-K.; Chang, Y.-W.; Chao, K.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:54Z |
Simultaneous layout migration and decomposition for double patterning technology
|
Hsu, C.-H.;Chang, Y.-W.;Nassif, S.R.; Hsu, C.-H.; Chang, Y.-W.; Nassif, S.R.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:54Z |
Routing for manufacturability and reliability
|
Chen, H.-Y.;Chang, Y.-W.; Chen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:54Z |
Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs
|
Lee, W.-P.;Marculescu, D.;Chang, Y.-W.; Lee, W.-P.; Marculescu, D.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:54Z |
Introduction
|
Stroud, C.E.;Wang, L.T.;Chang, Y.-W.; Stroud, C.E.; Wang, L.T.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:53Z |
Voltage-island partitioning and floorplanning under timing constraints
|
Lee, W.-P.;Liu, H.-Y.;Chang, Y.-W.; Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:53Z |
Voltage-Island partitioning and floorplanning under timing constraints
|
Lee, W.-P.;Liu, H.-Y.;Chang, Y.-W.; Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:53Z |
Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs
|
Chuang, Y.-L.;Lee, P.-W.;Chang, Y.-W.; Chuang, Y.-L.; Lee, P.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:08:26Z |
An Efficient Graph-Based Algorithm for ESD Current Path Analysis
|
C. H. Liu;H. Y. Liu;C. W. Lin;S. J. Chou;Y. W. Chang;S. Y. Kuo;S. Y. Yuan;Y. W. Chen; C. H. Liu; H. Y. Liu; C. W. Lin; S. J. Chou; Y. W. Chang; S. Y. Kuo; S. Y. Yuan; Y. W. Chen; SY-YEN KUO; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:51Z |
Maximally routable switch matrices for FPD design
|
Wu, Guang-Min; Chang, Yao-Wen; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:51Z |
Graph matching-based algorithms for FPGA segmentation design
|
YAO-WEN CHANG; Wong, D.F.; Lin, Jai-Ming; Chang, Yao-Wen |
| 臺大學術典藏 |
2018-09-10T07:03:50Z |
An optimal network-flow-based simultaneous diode and jumper insertion algorithm for antenna fixing
|
Jiang, Z.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:50Z |
A progressive-ILP based routing algorithm for cross-referencing biochips
|
Yuh, Ping-Hung; Sapatnekar, S.; Yang, Chia-Lin; Chang, Yao-Wen; YAO-WEN CHANG; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T07:03:50Z |
A new multilevel framework for large-scale interconnect-driven floorplanning
|
YAO-WEN CHANG; Lin, S.-C.; Chang, Y.-W.; Chen, T.-C. |
| 臺大學術典藏 |
2018-09-10T07:03:50Z |
Timing-driven routing for symmetrical-array-based FPGAs
|
Zhu, Kai; Chang, Yao-Wen; Wong, D.F.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:50Z |
Switch-matrix architecture and routing for FPDs
|
Wu, Guang-Min; Chang, Yao-Wen; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:49Z |
Full-chip routing considering double-via insertion
|
Chen, H.-Y.; Chiang, M.-F.; Chang, Y.-W.; Chen, L.; Han, B.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:49Z |
Effective wire models for X-architecture placement
|
Chen, T.-C.; Chuang, Y.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:49Z |
Constraint graph-based macro placement for modern mixed-size circuit designs
|
Chen, H.-C.; Chuang, Y.-L.; Chang, Y.-W.; Chang, Y.-C.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:49Z |
BioRoute: A network-flow-based routing algorithm for the synthesis of digital microfluidic biochips
|
Yuh, Ping-Hung;Yang, Chia-Lin;Chang, Yao-Wen; Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; YAO-WEN CHANG; Yang, Chia-Lin |
| 臺大學術典藏 |
2018-09-10T07:03:49Z |
Area-I/O flip-chip routing for chip-package co-design
|
Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:48Z |
NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints
|
Chen, T.-C.; Jiang, Z.-W.; Hsu, T.-C.; Chen, H.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:48Z |
Multilayer obstacle-avoiding rectilinear steiner tree construction based on spanning graphs
|
Lin, C.-W.;Huang, S.-L.;Hsu, K.-C.;Lee, M.-X.;Chang, Y.-W.; Lin, C.-W.; Huang, S.-L.; Hsu, K.-C.; Lee, M.-X.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:48Z |
Multi-layer global routing considering via and wire capacities
|
Hsu, C.-H.; Chen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:48Z |
MP-trees: A packing-based macro placement algorithm for modern mixed-size designs
|
Chen, T.-C.; Yuh, P.-H.; Chang, Y.-W.; Huang, F.-J.; Liu, T.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:48Z |
Metal-density-driven placement for CMP variation and routability
|
Chen, T.-C.; Cho, M.; Pan, D.Z.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:48Z |
Metal-density driven placement for CMP variation and routability
|
Chen, T.-C.; Cho, M.; Pan, D.Z.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:47Z |
Sensitivity-based multiple-Vt cell swapping for leakage power reduction
|
Lee, W.-P.; Liu, H.-Y.; Ho, K.-H.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:47Z |
Routing for chip-package-board co-design considering differential pairs
|
Fang, J.-W.; Ho, K.-H.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:47Z |
Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs
|
Jiang, Z.-W.; Su, B.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:47Z |
Predictive formulae for OPC with applications to lithography-friendly routing
|
Chen, T.-C.; Liao, G.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:37:57Z |
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits
|
Chin-Hsiung Hsu; Szu-Jui Chou; Jie-Hong R. Jiang; Yao-Wen Chang; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T06:31:04Z |
A network-flow-based RDL routing algorithmz for flip-chip design
|
Fang, J.-W.; Lin, I.-J.; Chang, Y.-W.; Wang, J.-H.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:04Z |
Graph-theoretic sufficient condition for FPGA/FPIC switch-module routability
|
Chang, Yao-Wen; Wong, D.F.; Wong, C.K.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:04Z |
Algorithms for an FPGA switch module routing problem with application to global routing
|
Thakur, S.; Chang, Y.-W.; Wong, D.F.; Muthukrishnan, S.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:03Z |
An optimal jumper-insertion algorithm for antenna avoidance/fixing
|
Su, B.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:03Z |
An integer linear programming based routing algorithm for flip-chip design
|
Fang, J.-W.; Hsu, C.-H.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:03Z |
An exact jumper-insertion algorithm for antenna violation avoidance/fixing considering routing obstacles
|
Su, B.-Y.; Chang, Y.-W.; Hu, J.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:03Z |
An efficient algorithm for statistical circuit optimization using Lagrangian relaxation
|
Lin, I.-J.; Chang, Y.-W.; YAO-WEN CHANG |
