| 臺大學術典藏 |
2018-09-10T07:36:54Z |
T-trees: A tree-based representation for temporal and three-dimensional floorplanning
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Yuh, P.-H.;Yang, C.-L.;Chang, Y.-W.; Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T07:36:54Z |
Spare-cell-aware multilevel analytical placement
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Jiang, Z.-W.;Hsu, M.-K.;Chang, Y.-W.;Chao, K.-Y.; Jiang, Z.-W.; Hsu, M.-K.; Chang, Y.-W.; Chao, K.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:54Z |
Simultaneous layout migration and decomposition for double patterning technology
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Hsu, C.-H.;Chang, Y.-W.;Nassif, S.R.; Hsu, C.-H.; Chang, Y.-W.; Nassif, S.R.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:54Z |
Routing for manufacturability and reliability
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Chen, H.-Y.;Chang, Y.-W.; Chen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:54Z |
Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs
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Lee, W.-P.;Marculescu, D.;Chang, Y.-W.; Lee, W.-P.; Marculescu, D.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:54Z |
Introduction
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Stroud, C.E.;Wang, L.T.;Chang, Y.-W.; Stroud, C.E.; Wang, L.T.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:53Z |
Voltage-island partitioning and floorplanning under timing constraints
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Lee, W.-P.;Liu, H.-Y.;Chang, Y.-W.; Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:53Z |
Voltage-Island partitioning and floorplanning under timing constraints
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Lee, W.-P.;Liu, H.-Y.;Chang, Y.-W.; Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:36:53Z |
Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs
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Chuang, Y.-L.;Lee, P.-W.;Chang, Y.-W.; Chuang, Y.-L.; Lee, P.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:08:26Z |
An Efficient Graph-Based Algorithm for ESD Current Path Analysis
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C. H. Liu;H. Y. Liu;C. W. Lin;S. J. Chou;Y. W. Chang;S. Y. Kuo;S. Y. Yuan;Y. W. Chen; C. H. Liu; H. Y. Liu; C. W. Lin; S. J. Chou; Y. W. Chang; S. Y. Kuo; S. Y. Yuan; Y. W. Chen; SY-YEN KUO; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:51Z |
Maximally routable switch matrices for FPD design
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Wu, Guang-Min; Chang, Yao-Wen; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:51Z |
Graph matching-based algorithms for FPGA segmentation design
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YAO-WEN CHANG; Wong, D.F.; Lin, Jai-Ming; Chang, Yao-Wen |
| 臺大學術典藏 |
2018-09-10T07:03:50Z |
An optimal network-flow-based simultaneous diode and jumper insertion algorithm for antenna fixing
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Jiang, Z.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:50Z |
A progressive-ILP based routing algorithm for cross-referencing biochips
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Yuh, Ping-Hung; Sapatnekar, S.; Yang, Chia-Lin; Chang, Yao-Wen; YAO-WEN CHANG; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T07:03:50Z |
A new multilevel framework for large-scale interconnect-driven floorplanning
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YAO-WEN CHANG; Lin, S.-C.; Chang, Y.-W.; Chen, T.-C. |
| 臺大學術典藏 |
2018-09-10T07:03:50Z |
Timing-driven routing for symmetrical-array-based FPGAs
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Zhu, Kai; Chang, Yao-Wen; Wong, D.F.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:50Z |
Switch-matrix architecture and routing for FPDs
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Wu, Guang-Min; Chang, Yao-Wen; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:49Z |
Full-chip routing considering double-via insertion
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Chen, H.-Y.; Chiang, M.-F.; Chang, Y.-W.; Chen, L.; Han, B.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:49Z |
Effective wire models for X-architecture placement
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Chen, T.-C.; Chuang, Y.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:49Z |
Constraint graph-based macro placement for modern mixed-size circuit designs
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Chen, H.-C.; Chuang, Y.-L.; Chang, Y.-W.; Chang, Y.-C.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:49Z |
BioRoute: A network-flow-based routing algorithm for the synthesis of digital microfluidic biochips
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Yuh, Ping-Hung;Yang, Chia-Lin;Chang, Yao-Wen; Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; YAO-WEN CHANG; Yang, Chia-Lin |
| 臺大學術典藏 |
2018-09-10T07:03:49Z |
Area-I/O flip-chip routing for chip-package co-design
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Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:48Z |
NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints
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Chen, T.-C.; Jiang, Z.-W.; Hsu, T.-C.; Chen, H.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:48Z |
Multilayer obstacle-avoiding rectilinear steiner tree construction based on spanning graphs
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Lin, C.-W.;Huang, S.-L.;Hsu, K.-C.;Lee, M.-X.;Chang, Y.-W.; Lin, C.-W.; Huang, S.-L.; Hsu, K.-C.; Lee, M.-X.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:48Z |
Multi-layer global routing considering via and wire capacities
|
Hsu, C.-H.; Chen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
