| 臺大學術典藏 |
2018-09-10T07:03:47Z |
Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs
|
Jiang, Z.-W.; Su, B.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T07:03:47Z |
Predictive formulae for OPC with applications to lithography-friendly routing
|
Chen, T.-C.; Liao, G.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:37:57Z |
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits
|
Chin-Hsiung Hsu; Szu-Jui Chou; Jie-Hong R. Jiang; Yao-Wen Chang; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T06:31:04Z |
A network-flow-based RDL routing algorithmz for flip-chip design
|
Fang, J.-W.; Lin, I.-J.; Chang, Y.-W.; Wang, J.-H.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:04Z |
Graph-theoretic sufficient condition for FPGA/FPIC switch-module routability
|
Chang, Yao-Wen; Wong, D.F.; Wong, C.K.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:04Z |
Algorithms for an FPGA switch module routing problem with application to global routing
|
Thakur, S.; Chang, Y.-W.; Wong, D.F.; Muthukrishnan, S.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:03Z |
An optimal jumper-insertion algorithm for antenna avoidance/fixing
|
Su, B.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:03Z |
An integer linear programming based routing algorithm for flip-chip design
|
Fang, J.-W.; Hsu, C.-H.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:03Z |
An exact jumper-insertion algorithm for antenna violation avoidance/fixing considering routing obstacles
|
Su, B.-Y.; Chang, Y.-W.; Hu, J.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:03Z |
An efficient algorithm for statistical circuit optimization using Lagrangian relaxation
|
Lin, I.-J.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:03Z |
A statistical approach to the timing-yield optimization of pipeline circuits
|
Hsu, C.-H.; Chou, S.-J.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:02Z |
Efficient multi-layer obstacle-avoiding rectilinear steiner tree construction
|
Lin, C.-W.; Huang, S.-L.; Hsu, K.-C.; Li, M.-X.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:02Z |
ECO timing optimization using spare cells
|
Chen, Y.-P.; Fang, J.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:02Z |
Challenges and solutions in modern VLSI placement
|
Jiang, Z.-W.; Chen, H.-.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:01Z |
Multilevel full-chip routing with testability and yield enhancement
|
Li, K.S.-M.; Chang, Y.-W.; Lee, C.-L.; Su, C.; Chen, J.E.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:01Z |
Multilevel full-chip gridless routing with applications to optical-proximity correction
|
Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:01Z |
MP-trees: A packing-based macro placement algorithm for mixed-size designs
|
Chen, T.-C.; Yuh, P.-H.; Chang, Y.-W.; Huang, F.-J.; Liu, D.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:01Z |
MB*-tree: A multilevel floorplanner for large-scale building-module design
|
Yang, H.H.; YAO-WEN CHANG; Chang, Y.-W.; Lee, H.-C. |
| 臺大學術典藏 |
2018-09-10T06:31:01Z |
Efficient obstacle-avoiding rectilinear steiner tree construction
|
Lin, C.-W.; Chen, S.-Y.; Li, C.-F.; Chang, Y.-W.; Yang, C.-L.; YAO-WEN CHANG; CHIA-LIN YANG |
| 臺大學術典藏 |
2018-09-10T06:31:00Z |
Power/ground network and floorplan cosynthesis for fast design convergence
|
Liu, C.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:31:00Z |
Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation
|
Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; Yang, Chia-Lin |
| 臺大學術典藏 |
2018-09-10T06:31:00Z |
Novel wire density driven full-chip routing for CMP variation control
|
Chen, H.-Y.; Chou, S.-J.; Wang, S.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:30:59Z |
X-architecture placement based on effective wire models
|
YAO-WEN CHANG; Chang, Y.-W.; Chuang, Y.-L.; Chen, T.-C. |
| 臺大學術典藏 |
2018-09-10T06:30:59Z |
Thermal-driven interconnect optimization by simultaneous gate and wire sizing
|
Lin, Y.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:30:59Z |
Temporal floorplanning using the three-dimensional transitive closure subGraph
|
Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; Yang, Chia-Lin |
