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Showing items 226-235 of 348  (35 Page(s) Totally)
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Institution Date Title Author
臺大學術典藏 2018-09-10T06:31:01Z Multilevel full-chip gridless routing with applications to optical-proximity correction Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T06:31:01Z MP-trees: A packing-based macro placement algorithm for mixed-size designs Chen, T.-C.; Yuh, P.-H.; Chang, Y.-W.; Huang, F.-J.; Liu, D.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T06:31:01Z MB*-tree: A multilevel floorplanner for large-scale building-module design Yang, H.H.; YAO-WEN CHANG; Chang, Y.-W.; Lee, H.-C.
臺大學術典藏 2018-09-10T06:31:01Z Efficient obstacle-avoiding rectilinear steiner tree construction Lin, C.-W.; Chen, S.-Y.; Li, C.-F.; Chang, Y.-W.; Yang, C.-L.; YAO-WEN CHANG; CHIA-LIN YANG
臺大學術典藏 2018-09-10T06:31:00Z Power/ground network and floorplan cosynthesis for fast design convergence Liu, C.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T06:31:00Z Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; Yang, Chia-Lin
臺大學術典藏 2018-09-10T06:31:00Z Novel wire density driven full-chip routing for CMP variation control Chen, H.-Y.; Chou, S.-J.; Wang, S.-L.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T06:30:59Z X-architecture placement based on effective wire models YAO-WEN CHANG; Chang, Y.-W.; Chuang, Y.-L.; Chen, T.-C.
臺大學術典藏 2018-09-10T06:30:59Z Thermal-driven interconnect optimization by simultaneous gate and wire sizing Lin, Y.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T06:30:59Z Temporal floorplanning using the three-dimensional transitive closure subGraph Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG; Yang, Chia-Lin

Showing items 226-235 of 348  (35 Page(s) Totally)
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