| 臺大學術典藏 |
2018-09-10T06:30:59Z |
Statistical circuit optimization considering device andinterconnect process variations
|
Lin, I.-J.; Ling, T.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:30:59Z |
Recent research and emerging challenges in physical design for manufacturability/reliability
|
Lin, C.-W.; Tsai, M.-C.; Lee, K.-Y.; Chen, T.-.; Wang, T.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T06:30:58Z |
X-route: An x-architecture full-chip multilevel router
|
Chang, C.-F.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:35Z |
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints
|
Chen, T.-C.; Jiang, Z.-W.; Hsu, T.-C.; Chen, H.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:35Z |
Universal switch modules for fpga design
|
Chang, Y.-W.;Wong, D.F.;Wong, C.K.; Chang, Y.-W.; Wong, D.F.; Wong, C.K.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:35Z |
On a new timing-driven routing tree problem
|
Chang, Yao-Wen;Wong, D.F.;Zhu, Kai;Wong, C.K.; Chang, Yao-Wen; Wong, D.F.; Zhu, Kai; Wong, C.K.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:35Z |
Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
|
Chen, Chung-Ping;Chang, Yao-Wen;Wong, D.F.; Chen, Chung-Ping; Chang, Yao-Wen; Wong, D.F.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:34Z |
Floorplan and power/ground network co-synthesis for fast design convergence
|
Liu, C.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:34Z |
Current path analysis for electrostatic discharge protection
|
Liu, H.-Y.; Lin, C.-W.; Chou, S.-J.; Tu, W.-T.; Liu, C.-H.; Chang, Y.-W.; Kuo, S.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:34Z |
Charge-based capacitance measurement for bias-dependent capacitance
|
YAO-WEN CHANG; Chang, Y.-W.; Chang, H.-W.; Lu, T.-C.; King, Y.-C.; Ting, W.; Ku, Y.-H.J.; Lu, C.-Y. |
| 臺大學術典藏 |
2018-09-10T05:58:34Z |
An optimal simultaneous diode/jumper insertion algorithm for antenna fixing
|
Jiang, Z.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:34Z |
An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles
|
Su, B.-Y.; Chang, Y.-W.; Hu, J.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:34Z |
A novel framework for multilevel full-chip gridless routing
|
Chen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:33Z |
Multilevel routing with jumper insertion for antenna avoidance
|
Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; YAO-WEN CHANG; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T05:58:33Z |
Modern floorplanning based on B*-tree and fast simulated annealing
|
Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:33Z |
Inductance extraction for general interconnect structures
|
Lai, C.-Y.; Jeng, S.-K.; Chang, Y.-W.; Tsai, C.-C.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:33Z |
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults
|
Li, K.S.-M.; Su, C.; Chang, Y.-W.; Lee, C.-L.; Chen, J.E.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:33Z |
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults
|
Li, K.S.-M.; Chang, Y.-W.; Su, C.; Lee, C.-L.; Chen, J.E.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:32Z |
RLC coupling-aware simulation and on-chip bus encoding for delay reduction
|
Tu, S.-W.; Chang, Y.-W.; Jou, J.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:32Z |
Reliable crosstalk-driven interconnect optimization
|
Jiang, I.H.-R.; Pan, S.-R.; Chang, Y.-W.; Jou, J.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:32Z |
Physical design for System-On-a-Chip
|
Chang, Y.-W.; Chen, T.-C.; Chen, H.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:32Z |
NTUplace2: A hybrid placer using partitioning and analytical techniques
|
Jiang, Z.-W.; Chen, T.-C.; Hsu, T.-C.; Chen, H.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:32Z |
Novel full-chip gridless routing considering double-via insertion
|
Chen, H.-Y.; Chiang, M.-F.; Chang, Y.-W.; Chen, L.; Han, B.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:31Z |
Voltage Island aware floorplanning for power and timing optimization
|
Lee, W.-P.;Liu, H.-Y.;Chang, Y.-W.; Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:31Z |
Simultaneous block and I/O buffer floorplanning for flip-chip design
|
Peng, C.-Y.; Chao, W.-C.; Chang, Y.-W.; Wang, J.-H.; YAO-WEN CHANG |
