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機構 日期 題名 作者
臺大學術典藏 2018-09-10T05:58:34Z An optimal simultaneous diode/jumper insertion algorithm for antenna fixing Jiang, Z.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:58:34Z An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles Su, B.-Y.; Chang, Y.-W.; Hu, J.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:58:34Z A novel framework for multilevel full-chip gridless routing Chen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:58:33Z Multilevel routing with jumper insertion for antenna avoidance Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; YAO-WEN CHANG; SAO-JIE CHEN
臺大學術典藏 2018-09-10T05:58:33Z Modern floorplanning based on B*-tree and fast simulated annealing Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:58:33Z Inductance extraction for general interconnect structures Lai, C.-Y.; Jeng, S.-K.; Chang, Y.-W.; Tsai, C.-C.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:58:33Z IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults Li, K.S.-M.; Su, C.; Chang, Y.-W.; Lee, C.-L.; Chen, J.E.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:58:33Z IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults Li, K.S.-M.; Chang, Y.-W.; Su, C.; Lee, C.-L.; Chen, J.E.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:58:32Z RLC coupling-aware simulation and on-chip bus encoding for delay reduction Tu, S.-W.; Chang, Y.-W.; Jou, J.-Y.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:58:32Z Reliable crosstalk-driven interconnect optimization Jiang, I.H.-R.; Pan, S.-R.; Chang, Y.-W.; Jou, J.-Y.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:58:32Z Physical design for System-On-a-Chip Chang, Y.-W.; Chen, T.-C.; Chen, H.-Y.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:58:32Z NTUplace2: A hybrid placer using partitioning and analytical techniques Jiang, Z.-W.; Chen, T.-C.; Hsu, T.-C.; Chen, H.-C.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:58:32Z Novel full-chip gridless routing considering double-via insertion Chen, H.-Y.; Chiang, M.-F.; Chang, Y.-W.; Chen, L.; Han, B.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:58:31Z Voltage Island aware floorplanning for power and timing optimization Lee, W.-P.;Liu, H.-Y.;Chang, Y.-W.; Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:58:31Z Simultaneous block and I/O buffer floorplanning for flip-chip design Peng, C.-Y.; Chao, W.-C.; Chang, Y.-W.; Wang, J.-H.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:23:31Z Design and analysis of FPGA/FPIC switch modules Chang, Yao-Wen;Wong, D.F.;Wong, C.K.; Chang, Yao-Wen; Wong, D.F.; Wong, C.K.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:23:30Z IMF: Interconnect-driven multilevel floorplanning for large-scale building-module designs Chen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:23:30Z Delay modeling for buffered RLY/RLC trees Wang, S.-L.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:23:30Z Crosstalk- and performance-driven multilevel full-chip routing Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Lee, D.-T.; YAO-WEN CHANG; SAO-JIE CHEN
臺大學術典藏 2018-09-10T05:23:30Z An exact jumper insertion algorithm for antenna effect avoidance/fixing Su, B.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:23:30Z A routing algorithm for flip-chip design Fang, J.-W.; Lin, I.-J.; Yuh, P.-H.; Chang, Y.-W.; Wang, J.-H.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:23:30Z FPGA global routing based on a new congestion metric Chang, Yao-Wen;Wong, D.F.;Wong, C.K.; Chang, Yao-Wen; Wong, D.F.; Wong, C.K.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:23:29Z Multilevel full-chip routing with testability and yield enhancement Li, K.S.-M.; Lee, C.-L.; Chang, Y.-W.; Su, C.; Chen, J.-E.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:23:29Z Multilevel full-chip routing for the X-based architecture Ho, T.-Y.; Chang, C.-F.; Chang, Y.-W.; Chen, S.-J.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:23:29Z Multilevel full-chip gridless routing considering optical proximity correction Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG

顯示項目 246-270 / 348 (共14頁)
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