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Taiwan Academic Institutional Repository >
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"yao wen chang"
Showing items 251-260 of 348 (35 Page(s) Totally)
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| 臺大學術典藏 |
2018-09-10T05:58:33Z |
Inductance extraction for general interconnect structures
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Lai, C.-Y.; Jeng, S.-K.; Chang, Y.-W.; Tsai, C.-C.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:33Z |
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults
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Li, K.S.-M.; Su, C.; Chang, Y.-W.; Lee, C.-L.; Chen, J.E.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:33Z |
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults
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Li, K.S.-M.; Chang, Y.-W.; Su, C.; Lee, C.-L.; Chen, J.E.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:32Z |
RLC coupling-aware simulation and on-chip bus encoding for delay reduction
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Tu, S.-W.; Chang, Y.-W.; Jou, J.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:32Z |
Reliable crosstalk-driven interconnect optimization
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Jiang, I.H.-R.; Pan, S.-R.; Chang, Y.-W.; Jou, J.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:32Z |
Physical design for System-On-a-Chip
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Chang, Y.-W.; Chen, T.-C.; Chen, H.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:32Z |
NTUplace2: A hybrid placer using partitioning and analytical techniques
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Jiang, Z.-W.; Chen, T.-C.; Hsu, T.-C.; Chen, H.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:32Z |
Novel full-chip gridless routing considering double-via insertion
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Chen, H.-Y.; Chiang, M.-F.; Chang, Y.-W.; Chen, L.; Han, B.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:31Z |
Voltage Island aware floorplanning for power and timing optimization
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Lee, W.-P.;Liu, H.-Y.;Chang, Y.-W.; Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:31Z |
Simultaneous block and I/O buffer floorplanning for flip-chip design
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Peng, C.-Y.; Chao, W.-C.; Chang, Y.-W.; Wang, J.-H.; YAO-WEN CHANG |
Showing items 251-260 of 348 (35 Page(s) Totally)
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