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"yao wen chang"的相關文件
顯示項目 256-265 / 348 (共35頁)
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| 臺大學術典藏 |
2018-09-10T05:58:32Z |
Physical design for System-On-a-Chip
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Chang, Y.-W.; Chen, T.-C.; Chen, H.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:32Z |
NTUplace2: A hybrid placer using partitioning and analytical techniques
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Jiang, Z.-W.; Chen, T.-C.; Hsu, T.-C.; Chen, H.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:32Z |
Novel full-chip gridless routing considering double-via insertion
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Chen, H.-Y.; Chiang, M.-F.; Chang, Y.-W.; Chen, L.; Han, B.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:31Z |
Voltage Island aware floorplanning for power and timing optimization
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Lee, W.-P.;Liu, H.-Y.;Chang, Y.-W.; Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:31Z |
Simultaneous block and I/O buffer floorplanning for flip-chip design
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Peng, C.-Y.; Chao, W.-C.; Chang, Y.-W.; Wang, J.-H.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:31Z |
Design and analysis of FPGA/FPIC switch modules
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Chang, Yao-Wen;Wong, D.F.;Wong, C.K.; Chang, Yao-Wen; Wong, D.F.; Wong, C.K.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:30Z |
IMF: Interconnect-driven multilevel floorplanning for large-scale building-module designs
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Chen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:30Z |
Delay modeling for buffered RLY/RLC trees
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Wang, S.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:30Z |
Crosstalk- and performance-driven multilevel full-chip routing
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Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Lee, D.-T.; YAO-WEN CHANG; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T05:23:30Z |
An exact jumper insertion algorithm for antenna effect avoidance/fixing
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Su, B.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
顯示項目 256-265 / 348 (共35頁)
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