| 臺大學術典藏 |
2018-09-10T05:23:30Z |
A routing algorithm for flip-chip design
|
Fang, J.-W.; Lin, I.-J.; Yuh, P.-H.; Chang, Y.-W.; Wang, J.-H.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:30Z |
FPGA global routing based on a new congestion metric
|
Chang, Yao-Wen;Wong, D.F.;Wong, C.K.; Chang, Yao-Wen; Wong, D.F.; Wong, C.K.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:29Z |
Multilevel full-chip routing with testability and yield enhancement
|
Li, K.S.-M.; Lee, C.-L.; Chang, Y.-W.; Su, C.; Chen, J.-E.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:29Z |
Multilevel full-chip routing for the X-based architecture
|
Ho, T.-Y.; Chang, C.-F.; Chang, Y.-W.; Chen, S.-J.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:29Z |
Multilevel full-chip gridless routing considering optical proximity correction
|
Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:29Z |
Modern floorplanning based on fast simulated annealing
|
Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:28Z |
TCG: A transitive closure graph-based representation for general floorplans
|
Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:28Z |
SoC test scheduling using the B*-tree based floorplanning technique
|
Wuu, J.-Y.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:28Z |
Rlc coupling-Aware simulation for on-chip buses and their encoding for delay reduction
|
Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:28Z |
Placement with symmetry constraints for analog layout design using TCG-S
|
Lin, J.-M.; Wu, G.-M.; Chang, Y.-W.; Chuang, J.-H.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:20:41Z |
Reconfigurable platform for content science research
|
Shih, C.-S.; Yang, C.-L.; Ku, M.-K.; Kuo, T.-W.; Chien, S.-Y.; Chang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN; Shih, Chi-Sheng; Yang, Chia-Lin; TEI-WEI KUO; YAO-WEN CHANG; SHAO-YI CHIEN |
| 臺大學術典藏 |
2018-09-10T04:53:45Z |
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization
|
Cheng, Y.-H.; Chang, Y.-W.; Cheng, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:45Z |
Efficient power/ground network analysis for power integrity-driven design methodology
|
Wu, S.-W.; Chang, Y.-W.; Wu, S.-W.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:45Z |
A reusable methodology for non-slicing floorplanning
|
Hsu, J.-M.; Chang, Y.-W.; Hsu, J.-M.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:45Z |
New global routing algorithm for FPGAs
|
Chang, Yao-Wen;Thakur, Shashidhar;Zhu, Kai;Wong, D.F.; Chang, Yao-Wen; Thakur, Shashidhar; Zhu, Kai; Wong, D.F.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
RLC effects on worst-case switching pattern for on-chip buses
|
Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Universal switch blocks for three-dimensional FPGA design
|
Wu, G.-M.; Shyu, M.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Temporal floorplanning using the T-tree formulation
|
Yuh, P.-H.;Yang, C.-L.;Chang, Y.-W.; Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Temporal floorplanning using 3D-subTCG
|
Yuh, P.-H.;Yang, C.-L.;Chang, Y.-W.;Chen, H.-L.; Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; Chen, H.-L.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
TCG-S: Orthogonal coupling of P*-admissible representations for general floorplans
|
Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Placement with alignment and performance constraints using the B*-tree representation
|
Wu, M.-C.; Chang, Y.-W.; Wu, M.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Multilevel routing with jumper insertion for antenna avoidance
|
Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Multilevel routing with antenna avoidance
|
Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Layout techniques for on-chip interconnect inductance reduction
|
Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:33:03Z |
Switch module design with application to two-dimensional segmentation design
|
Zhu, Kai; Wong, D.F.; Chang, Yao-Wen; YAO-WEN CHANG |
