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機構 日期 題名 作者
臺大學術典藏 2018-09-10T05:23:29Z Modern floorplanning based on fast simulated annealing Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:23:28Z TCG: A transitive closure graph-based representation for general floorplans Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:23:28Z SoC test scheduling using the B*-tree based floorplanning technique Wuu, J.-Y.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:23:28Z Rlc coupling-Aware simulation for on-chip buses and their encoding for delay reduction Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:23:28Z Placement with symmetry constraints for analog layout design using TCG-S Lin, J.-M.; Wu, G.-M.; Chang, Y.-W.; Chuang, J.-H.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T05:20:41Z Reconfigurable platform for content science research Shih, C.-S.; Yang, C.-L.; Ku, M.-K.; Kuo, T.-W.; Chien, S.-Y.; Chang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN; Shih, Chi-Sheng; Yang, Chia-Lin; TEI-WEI KUO; YAO-WEN CHANG; SHAO-YI CHIEN
臺大學術典藏 2018-09-10T04:53:45Z Integrating buffer planning with floorplanning for simultaneous multi-objective optimization Cheng, Y.-H.; Chang, Y.-W.; Cheng, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:53:45Z Efficient power/ground network analysis for power integrity-driven design methodology Wu, S.-W.; Chang, Y.-W.; Wu, S.-W.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:53:45Z A reusable methodology for non-slicing floorplanning Hsu, J.-M.; Chang, Y.-W.; Hsu, J.-M.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:53:45Z New global routing algorithm for FPGAs Chang, Yao-Wen;Thakur, Shashidhar;Zhu, Kai;Wong, D.F.; Chang, Yao-Wen; Thakur, Shashidhar; Zhu, Kai; Wong, D.F.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:53:44Z RLC effects on worst-case switching pattern for on-chip buses Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:53:44Z Universal switch blocks for three-dimensional FPGA design Wu, G.-M.; Shyu, M.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:53:44Z Temporal floorplanning using the T-tree formulation Yuh, P.-H.;Yang, C.-L.;Chang, Y.-W.; Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:53:44Z Temporal floorplanning using 3D-subTCG Yuh, P.-H.;Yang, C.-L.;Chang, Y.-W.;Chen, H.-L.; Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; Chen, H.-L.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:53:44Z TCG-S: Orthogonal coupling of P*-admissible representations for general floorplans Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:53:44Z Placement with alignment and performance constraints using the B*-tree representation Wu, M.-C.; Chang, Y.-W.; Wu, M.-C.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:53:44Z Multilevel routing with jumper insertion for antenna avoidance Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:53:44Z Multilevel routing with antenna avoidance Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:53:44Z Layout techniques for on-chip interconnect inductance reduction Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:33:03Z Switch module design with application to two-dimensional segmentation design Zhu, Kai; Wong, D.F.; Chang, Yao-Wen; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:33:03Z A Fast Crosstalk- and Performance-Driven Multilevel Routing System Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Lee, D.T.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:33:02Z Rectilinear block placement using B*-trees Wu, G.-M.; Chang, Y.-C.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:33:02Z Noise-aware buffer planning for interconnect-driven floorplanning Li, S.-M.; Cherng, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:33:02Z Multilevel floorplanning/placement for large-scale modules using B*-trees YAO-WEN CHANG; Yang, H.H.; Hsu, J.-M.; Chang, Y.-W.; Lee, H.-C.
臺大學術典藏 2018-09-10T04:33:02Z Graph matching-based algorithms for array-based FPGA segmentation design and routing Lin, J.-M.; Pan, S.-R.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:33:02Z Simultaneous floorplanning and buffer block planning Hui-Ru Jiang, I.; Chang, Y.-W.; Jou, J.-Y.; Chao, K.-Y.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:12:54Z A novel framework for multilevel routing considering routability and performance Lin, S.-P.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:12:53Z Module placement with boundary constraints using B*-trees Lin, J.-M.; Yi, H.-E.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:12:53Z Inductance modeling for on-chip interconnects Tu, S.-W.; Shen, W.-Z.; Chang, Y.-W.; Chen, T.-C.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:12:53Z Formulae for performance optimization and their applications to interconnect-driven floorplanning Chang, N.C.-Y.; Chang, Y.-W.; Jian, I.H.-R.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:12:53Z Comment on "generic universal switch blocks" Fan, H.; Wu, Y.-L.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:12:53Z Arbitrary convex and concave rectilinear module packing using TCG Lin, J.-M.; Chen, H.-L.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:12:53Z Arbitrarily shaped rectilinear module placement using the transitive closure graph representation Lin, J.-M.; Chen, H.-L.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T04:12:52Z Performance-driven placement for dynamically reconfigurable FPGAs Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; Wu, Guang-Ming; Lin, Jai-Ming; Chang, Yao-Wen; YAO-WEN CHANG
臺大學術典藏 2018-09-10T03:47:58Z Generic ILP-based approaches for time-multiplexed FPGA partitioning Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T03:47:57Z Performance optimization by wire and buffer sizing under the transmission line model Chen, T.-C.; Pan, S.-R.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T03:29:38Z Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; YAO-WEN CHANG
臺大學術典藏 2018-09-10T03:29:38Z Crosstalk-constrained performance optimization by using wire sizing and perturbation Pan, Song-Ra; Chang, Yao-Wen; YAO-WEN CHANG
臺大學術典藏 2018-09-10T03:29:38Z B*-trees: a new representation for non-slicing floorplans Chang, Yun-Chih; Chang, Yao-Wen; Wu, Guang-Ming; Wu, Shu-Wei; YAO-WEN CHANG
臺大學術典藏 2018-09-10T03:29:38Z Architecture-driven metric for simultaneous placement and global routing for FPGAs YAO-WEN CHANG; Chang, Yu-Tsang; Chang, Yao-Wen
臺大學術典藏 2018-09-10T03:29:37Z Timing-driven routing for symmetrical array-based FPGAs Chang, Y.-W.; Zhu, K.; Wong, D.F.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T03:29:37Z Rectilinear block placement using B*-trees Wu, Guang-Ming; Chang, Yun-Chih; Chang, Yao-Wen; YAO-WEN CHANG
臺大學術典藏 2018-09-10T03:29:37Z Optimal reliable crosstalk-driven interconnect optimization Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; Jou, Jing-Yang; YAO-WEN CHANG
臺大學術典藏 2018-09-10T03:29:37Z Generic universal switch blocks Shyu, M.; Wu, G.-M.; Chang, Y.-D.; Chang, Y.-W.; YAO-WEN CHANG
臺大學術典藏 2018-09-10T03:29:37Z Crosstalkdriven interconnect optimization by simultaneous gate and wire sizing Jiang, I.H.R.; Chang, Y.W.; Jou, J.Y.; YAO-WEN CHANG
東海大學 2015 磁振造影之多視角乳房腫瘤輪廓描繪 張耀文; Yao-Wen Chang
國立交通大學 2014-12-12T02:29:38Z 在平面規劃階段的電源/接地網合成 吳素緯; Su-Wei Wu; 莊仁輝; 張耀文; Jen-Hui Chuang; Yao-Wen Chang
國立交通大學 2014-12-12T02:27:53Z 以三維子遞移封閉圖處理時序性平面規劃 陳信隆; HsinLung Chen; 莊仁輝; 張耀文; Jen-Hui Chuang; Yao-Wen Chang
國立交通大學 2014-12-12T02:27:53Z 利用遞移封閉圖表示法處理超大型積體電路之平面規劃 林家民; Jai-Ming Lin; 莊仁輝; 張耀文; Jen-Hui Chuang; Yao-Wen Chang
國立交通大學 2014-12-12T02:27:45Z 同步考慮面積、時序、雜訊及壅塞最佳化之整合緩衝器及平面規劃 程益輝; Yi-Hui Cheng; 莊仁輝; 張耀文; Jen-Hui Chuang; Yao-Wen Chang

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