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"yao wen chang"的相關文件
顯示項目 281-290 / 348 (共35頁)
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| 臺大學術典藏 |
2018-09-10T04:53:44Z |
RLC effects on worst-case switching pattern for on-chip buses
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Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Universal switch blocks for three-dimensional FPGA design
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Wu, G.-M.; Shyu, M.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Temporal floorplanning using the T-tree formulation
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Yuh, P.-H.;Yang, C.-L.;Chang, Y.-W.; Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Temporal floorplanning using 3D-subTCG
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Yuh, P.-H.;Yang, C.-L.;Chang, Y.-W.;Chen, H.-L.; Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; Chen, H.-L.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
TCG-S: Orthogonal coupling of P*-admissible representations for general floorplans
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Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Placement with alignment and performance constraints using the B*-tree representation
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Wu, M.-C.; Chang, Y.-W.; Wu, M.-C.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Multilevel routing with jumper insertion for antenna avoidance
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Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Multilevel routing with antenna avoidance
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Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; Ho, T.-Y.; Chang, Y.-W.; Chen, S.-J.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Layout techniques for on-chip interconnect inductance reduction
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Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:33:03Z |
Switch module design with application to two-dimensional segmentation design
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Zhu, Kai; Wong, D.F.; Chang, Yao-Wen; YAO-WEN CHANG |
顯示項目 281-290 / 348 (共35頁)
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