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教育部委托研究计画 计画执行:国立台湾大学图书馆
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"yao wen chang"的相关文件
显示项目 296-305 / 348 (共35页)
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| 臺大學術典藏 |
2018-09-10T04:33:02Z |
Simultaneous floorplanning and buffer block planning
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Hui-Ru Jiang, I.; Chang, Y.-W.; Jou, J.-Y.; Chao, K.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:54Z |
A novel framework for multilevel routing considering routability and performance
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Lin, S.-P.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:53Z |
Module placement with boundary constraints using B*-trees
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Lin, J.-M.; Yi, H.-E.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:53Z |
Inductance modeling for on-chip interconnects
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Tu, S.-W.; Shen, W.-Z.; Chang, Y.-W.; Chen, T.-C.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:53Z |
Formulae for performance optimization and their applications to interconnect-driven floorplanning
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Chang, N.C.-Y.; Chang, Y.-W.; Jian, I.H.-R.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:53Z |
Comment on "generic universal switch blocks"
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Fan, H.; Wu, Y.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:53Z |
Arbitrary convex and concave rectilinear module packing using TCG
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Lin, J.-M.; Chen, H.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:53Z |
Arbitrarily shaped rectilinear module placement using the transitive closure graph representation
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Lin, J.-M.; Chen, H.-L.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:12:52Z |
Performance-driven placement for dynamically reconfigurable FPGAs
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Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; Wu, Guang-Ming; Lin, Jai-Ming; Chang, Yao-Wen; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T03:47:58Z |
Generic ILP-based approaches for time-multiplexed FPGA partitioning
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Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG |
显示项目 296-305 / 348 (共35页)
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