| 國立交通大學 |
2019-04-02T06:01:07Z |
A NOVEL LIQUID-PACKAGING TECHNOLOGY FOR HIGHLY RELIABLE UV-LED ENCAPSULATION
|
Zhang, Wen-Hua; Lin, Wei-Keng; Yeh, Chih-Ting; Chiang, Song-Bor; Jao, Chih-Sheng |
| 國立交通大學 |
2019-04-02T06:00:28Z |
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection
|
Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2019-04-02T05:58:21Z |
Luminescence material characterizations on laser-phosphor lighting techniques
|
Yeh, Chih-Ting; Chou, Yen-, I; Yang, Kai-Shing; Wu, Shih-Kuo; Wang, Chi-Chuang |
| 國立交通大學 |
2018-08-21T05:52:53Z |
A novel oxidized composite braided wires wick structure applicable for ultra-thin flattened heat pipes
|
Yang, Kai-Shing; Tu, Cheng-Wei; Zhang, Wen-Hua; Yeh, Chih-Ting; Wang, Chi-Chuan |
| 國立交通大學 |
2017-04-21T06:55:40Z |
An experimental and analytical investigation of the photo-thermal-electro characteristics of a high power InGaN LED module
|
Yang, Kai-Shing; Ding, Wei-Ting; Yeh, Chih-Ting; Lee, Ming-Tsang; Wang, Chi-Chuan |
| 國立交通大學 |
2017-04-21T06:50:01Z |
Design of Power-Rail ESD Clamp Circuit with Adjustable Holding Voltage against Mis-trigger or Transient-Induced Latch-On Events
|
Yeh, Chih-Ting; Liang, Yung-Chih; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:49:53Z |
Layout Optimization on ESD Diodes for Giga-Hz RF and High-Speed I/O Circuits
|
Yeh, Chih-Ting; Liang, Yung-Chih; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:49:47Z |
Area-Efficient Power-Rail ESD Clamp Circuit with SCR Device Embedded into ESD-Transient Detection Circuit in a 65nm CMOS Process
|
Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:49:46Z |
Resistor-Less Power-Rail ESD Clamp Circuit with Ultra-Low Leakage Current in 65nm CMOS Process
|
Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2015-11-26T01:05:38Z |
全金屬矽化物互補式金氧半奈米晶片之靜電放電防護電路設計與實現
|
葉致廷; Yeh, Chih-Ting; 柯明道; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-12T02:51:27Z |
三端點與四端點的射頻金氧半電晶體模型參數萃取方法之建立及等效電路模擬之驗證
|
葉致廷; Yeh, Chih-Ting; 郭治群; Jyh-Chyurn Guo |
| 國立交通大學 |
2014-12-12T01:33:39Z |
奈米線蕭特基二極體於生醫感測研究
|
葉治廷; Yeh, Chih-Ting; 許鉦宗; Sheu, Jeng-Tzong |
| 國立交通大學 |
2014-12-08T15:47:57Z |
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection
|
Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:35:55Z |
On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology
|
Ker, Ming-Dou; Yeh, Chih-Ting |
| 國立交通大學 |
2014-12-08T15:30:24Z |
High Area-Efficient ESD Clamp Circuit With Equivalent RC-Based Detection Mechanism in a 65-nm CMOS Process
|
Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:29:54Z |
PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit
|
Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:28:28Z |
Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology
|
Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:24:11Z |
Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology
|
Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:23:37Z |
Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications
|
Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:22:20Z |
New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology
|
Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:09:00Z |
A New Three-Dimensional Capacitor Model for Accurate Simulation of Parasitic Capacitances in Nanoscale MOSFETs
|
Guo, Jyh-Chyurn; Yeh, Chih-Ting |
| 國立交通大學 |
2014-12-08T15:06:51Z |
Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits
|
Yeh, Chih-Ting; Ker, Ming-Dou; Liang, Yung-Chih |
| 國立臺灣大學 |
2014 |
利用乙氧基聚乙烯亞胺陰極介面層與石墨烯陰極製備倒置型有機太陽能電池及其元件特性分析
|
葉治鼎; Yeh, Chih-Ting |
| 國立政治大學 |
2012 |
手機晶片業者技術佈局之研究
|
葉治廷; Yeh, Chih Ting |
