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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"yeh chih ting"的相關文件
顯示項目 1-10 / 24 (共3頁)
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| 國立交通大學 |
2019-04-02T06:01:07Z |
A NOVEL LIQUID-PACKAGING TECHNOLOGY FOR HIGHLY RELIABLE UV-LED ENCAPSULATION
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Zhang, Wen-Hua; Lin, Wei-Keng; Yeh, Chih-Ting; Chiang, Song-Bor; Jao, Chih-Sheng |
| 國立交通大學 |
2019-04-02T06:00:28Z |
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection
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Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2019-04-02T05:58:21Z |
Luminescence material characterizations on laser-phosphor lighting techniques
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Yeh, Chih-Ting; Chou, Yen-, I; Yang, Kai-Shing; Wu, Shih-Kuo; Wang, Chi-Chuang |
| 國立交通大學 |
2018-08-21T05:52:53Z |
A novel oxidized composite braided wires wick structure applicable for ultra-thin flattened heat pipes
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Yang, Kai-Shing; Tu, Cheng-Wei; Zhang, Wen-Hua; Yeh, Chih-Ting; Wang, Chi-Chuan |
| 國立交通大學 |
2017-04-21T06:55:40Z |
An experimental and analytical investigation of the photo-thermal-electro characteristics of a high power InGaN LED module
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Yang, Kai-Shing; Ding, Wei-Ting; Yeh, Chih-Ting; Lee, Ming-Tsang; Wang, Chi-Chuan |
| 國立交通大學 |
2017-04-21T06:50:01Z |
Design of Power-Rail ESD Clamp Circuit with Adjustable Holding Voltage against Mis-trigger or Transient-Induced Latch-On Events
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Yeh, Chih-Ting; Liang, Yung-Chih; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:49:53Z |
Layout Optimization on ESD Diodes for Giga-Hz RF and High-Speed I/O Circuits
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Yeh, Chih-Ting; Liang, Yung-Chih; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:49:47Z |
Area-Efficient Power-Rail ESD Clamp Circuit with SCR Device Embedded into ESD-Transient Detection Circuit in a 65nm CMOS Process
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Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:49:46Z |
Resistor-Less Power-Rail ESD Clamp Circuit with Ultra-Low Leakage Current in 65nm CMOS Process
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Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2015-11-26T01:05:38Z |
全金屬矽化物互補式金氧半奈米晶片之靜電放電防護電路設計與實現
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葉致廷; Yeh, Chih-Ting; 柯明道; Ker, Ming-Dou |
顯示項目 1-10 / 24 (共3頁)
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