English  |  正體中文  |  简体中文  |  0  
???header.visitor??? :  52609055    ???header.onlineuser??? :  898
???header.sponsordeclaration???
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
???ui.leftmenu.abouttair???

???ui.leftmenu.bartitle???

???index.news???

???ui.leftmenu.copyrighttitle???

???ui.leftmenu.link???

"yeh chih ting"???jsp.browse.items-by-author.description???

???jsp.browse.items-by-author.back???
???jsp.browse.items-by-author.order1??? ???jsp.browse.items-by-author.order2???

Showing items 11-24 of 24  (1 Page(s) Totally)
1 
View [10|25|50] records per page

Institution Date Title Author
國立交通大學 2014-12-12T02:51:27Z 三端點與四端點的射頻金氧半電晶體模型參數萃取方法之建立及等效電路模擬之驗證 葉致廷; Yeh, Chih-Ting; 郭治群; Jyh-Chyurn Guo
國立交通大學 2014-12-12T01:33:39Z 奈米線蕭特基二極體於生醫感測研究 葉治廷; Yeh, Chih-Ting; 許鉦宗; Sheu, Jeng-Tzong
國立交通大學 2014-12-08T15:47:57Z Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection Yeh, Chih-Ting; Ker, Ming-Dou
國立交通大學 2014-12-08T15:35:55Z On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology Ker, Ming-Dou; Yeh, Chih-Ting
國立交通大學 2014-12-08T15:30:24Z High Area-Efficient ESD Clamp Circuit With Equivalent RC-Based Detection Mechanism in a 65-nm CMOS Process Yeh, Chih-Ting; Ker, Ming-Dou
國立交通大學 2014-12-08T15:29:54Z PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit Yeh, Chih-Ting; Ker, Ming-Dou
國立交通大學 2014-12-08T15:28:28Z Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology Yeh, Chih-Ting; Ker, Ming-Dou
國立交通大學 2014-12-08T15:24:11Z Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology Yeh, Chih-Ting; Ker, Ming-Dou
國立交通大學 2014-12-08T15:23:37Z Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications Yeh, Chih-Ting; Ker, Ming-Dou
國立交通大學 2014-12-08T15:22:20Z New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology Yeh, Chih-Ting; Ker, Ming-Dou
國立交通大學 2014-12-08T15:09:00Z A New Three-Dimensional Capacitor Model for Accurate Simulation of Parasitic Capacitances in Nanoscale MOSFETs Guo, Jyh-Chyurn; Yeh, Chih-Ting
國立交通大學 2014-12-08T15:06:51Z Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits Yeh, Chih-Ting; Ker, Ming-Dou; Liang, Yung-Chih
國立臺灣大學 2014 利用乙氧基聚乙烯亞胺陰極介面層與石墨烯陰極製備倒置型有機太陽能電池及其元件特性分析 葉治鼎; Yeh, Chih-Ting
國立政治大學 2012 手機晶片業者技術佈局之研究 葉治廷; Yeh, Chih Ting

Showing items 11-24 of 24  (1 Page(s) Totally)
1 
View [10|25|50] records per page