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Showing items 1-7 of 7 (1 Page(s) Totally)
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| 國立交通大學 |
2015-07-21T08:29:26Z |
Reliability-Driven Chip-Level Design for High-Frequency Digital Microfluidic Biochips
|
Yu, Shang-Tsung; Yeh, Sheng-Han; Ho, Tsung-Yi |
| 國立成功大學 |
2015-04 |
Reliability-Driven Chip-Level Design for High-Frequency Digital Microfluidic Biochips
|
Yu, Shang-Tsung; Yeh, Sheng-Han; Ho, Tsung-Yi |
| 國立成功大學 |
2014-09 |
Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips
|
Yeh, Sheng-Han; Chang, Jia-Wen; Huang, Tsung-Wei; Yu, Shang-Tsung; Ho, Tsung-Yi |
| 國立成功大學 |
2013-11 |
An ILP-based Routing Algorithm for Pin-Constrained EWOD Chips With Obstacle Avoidance
|
Chang, Jia-Wen; Yeh, Sheng-Han; Huang, Tsung-Wei; Ho, Tsung-Yi |
| 國立成功大學 |
2013-08-27 |
針對可靠的針腳限制介電濕潤晶片之考量電壓的晶片層級設計
|
葉昇翰; Yeh, Sheng-Han |
| 國立成功大學 |
2013-02-01 |
Integrated Fluidic-Chip Co-Design Methodology for Digital Microfluidic Biochips
|
Chang, Jia-Wen; Yeh, Sheng-Han; Huang, Tsung-Wei; Ho, Tsung-Yi |
| 國立成功大學 |
2012-11 |
Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips
|
Yeh, Sheng-Han; Chang, Jia-Wen; Huang, Tsung-Wei; Ho, Tsung-Yi |
Showing items 1-7 of 7 (1 Page(s) Totally)
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