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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
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Showing items 41-50 of 79  (8 Page(s) Totally)
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Institution Date Title Author
國立高雄大學 2009-03 The Impact of Strain Technology on FUSI Gate SOI CMOSFET Yeh, Wen-Kuan; Wang, Jean-An; Tsai, Ming-Hsing; Lin, Chien-Ting; Chen, Po-Ying
國立成功大學 2008-11 Significantly improving sub-90 nm CMOSFET performances with notch-gate enhanced high tensile-stress contact etch stop layer Hsu, Chia-Wei; Fang, Yean-Kuen; Yeh, Wen-Kuan; Lin, Chien-Ting
國立高雄大學 2008-10 Significant improvement of 45 nm and beyond complementary metal oxide semiconductor field effect transistor performance with fully silicided and ultimate spacer process technology Hsu, Chia-Wei; Fang, Yean-Kuen; Lin, Chien-Ting; Yeh, Wen-Kuan; Hsu, Che-Hua; Lai, Chieh-Ming; Cheng, Li-Wei; Ma, Mike
國立成功大學 2008-09-01 Significant improvement of 45 nm and beyond complementary metal oxide semiconductor field effect transistor performance with fully silicided and ultimate spacer process technology Hsu, Chia-Wei; Fang, Yean-Kuen; Lin, Chien-Ting; Yeh, Wen-Kuan; Hsu, Che-Hua; Lai, Chieh-Ming; Cheng, Li-Wei; Ma, Mike
國立成功大學 2008-08 A high current gain gate-controlled lateral bipolar junction transistor with 90 nm CMOS technology for future RF SoC applications Chen, Shuo-Mao; Fang, Yean-Kuen; Yeh, Wen-Kuan; Lee, I. C.; Chiang, Yen-Ting
國立高雄大學 2008-07 Significantly improving sub-90 nm CMOSFET performances with notch-gate enhanced high tensile-stress contact etch stop layer Hsu, Chia-Wei; Fang, Yean-Kuen; Yeh, Wen-Kuan; Lin, Chien-Ting
國立高雄大學 2008 A high current gain gate-controlled lateral bipolar junction transistor with 90 nm CMOS technology for future RF SoC applications Chen, Shuo-Mao; Fang, Yean-Kuen; Yeh, Wen-Kuan; Lee, I.C.; Chiang, Yen-Ting
國立高雄大學 2008 The impact of stain technology on FUSI gate SOI CMOSFET and device performance enhancement for 45nm node and beyond Yeh, Wen-Kuan; Wang, Jean-An; Lin, Chien-Ting; Cheng, Li-Wei; Ma, Mike
國立高雄大學 2007-07 The impact of mobility enhanced technology on device performance and reliability for sub-90nm SOI nMOSFETs Yeh, Wen-Kuan
國立高雄大學 2007-05 Impacts of notched-gate structure on contact etch stop layer (CESL) stressed 90-nm nMOSFET Lin, Chien-Ting; Fang, Yean-Kuen; Yeh, Wen-Kuan; Lai, Chieh-Ming; Hsu, Che-Hua; Cheng, Li-Wei; Ma, Guang-Hwa

Showing items 41-50 of 79  (8 Page(s) Totally)
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