| 臺大學術典藏 |
2018-09-10T09:25:26Z |
An X-band Full-360o Reflection Type Phase Shifter with low insertion loss
|
Wei-Tsung Li;Yen-Hung Kuo;Jeng-Han Tsai;Yi-Ming Wu;Tain-Wei Huang; Wei-Tsung Li; Yen-Hung Kuo; Jeng-Han Tsai; Yi-Ming Wu; Tain-Wei Huang; TIAN-WEI HUANG |
| 臺大學術典藏 |
2018-09-10T09:25:25Z |
Design and Analysis of Digital-Assisted Bandwidth-Enhanced Miller Divider in 0.18-μm CMOS Process
|
Yen-Hung Kuo;Jeng-Han Tsai;Tian-Wei Huang;Huei Wang; Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang; Huei Wang; TIAN-WEI HUANG; HUEI WANG |
| 臺大學術典藏 |
2018-09-10T09:25:25Z |
A Digital-Calibrated Transmitter-to-Receiver Isolator in Radar Applications
|
Yen-Hung Kuo;Jeng-Han Tsai;Tian-Wei Huang; Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang; TIAN-WEI HUANG |
| 臺大學術典藏 |
2018-09-10T08:47:17Z |
An Ultra Low-Power 24 GHz Phase-Lock-Loop with Low Phase-Noise VCO Embedded in 0.18μm CMOS Process
|
Yu-Hsuan Lin; Jeng-Han Tsai; Yen-Hung Kuo; Tian-Wei Huang; TIAN-WEI HUANG |
| 臺大學術典藏 |
2018-09-10T08:47:17Z |
A V-band VCO using fT-Doubling Technique in 0.18-um CMOS
|
Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang; Huei Wang; TIAN-WEI HUANG |
| 臺大學術典藏 |
2018-09-10T08:47:16Z |
Design and Analysis of A 77.3 % Locking Range Divide-by-4 Frequency Divider
|
Yen-Hung Kuo; Jeng-Han Tsai; Hong-Yeh Chang; Tian-Wei Huang; TIAN-WEI HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:03Z |
Admittance-Transforming Injection-Locked Frequency Divider and Low-Supply-Voltage Current Mode Logic Divider
|
Yen-Hung Kuo;Jeng-Han Tsai;Wei-Hung Chou;Tian-Wei Huang; Yen-Hung Kuo; Jeng-Han Tsai; Wei-Hung Chou; Tian-Wei Huang; TIAN-WEI HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:03Z |
A 24-GHz 3.8-dB NF Low-Noise Amplifier with Built-In Linearizer
|
Yen-Hung Kuo;Jeng-Han Tsai;Wei-Hung Chou;Tian-Wei Huang; Yen-Hung Kuo; Jeng-Han Tsai; Wei-Hung Chou; Tian-Wei Huang; TIAN-WEI HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:02Z |
A 1.5-mW, 23.6% Frequency Locking Range, 24-GHz Injection-Locked Frequency Divider
|
Yen-Hung Kuo;Jeng-Han Tsai;Tian-Wei Huang; Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang; TIAN-WEI HUANG |
| 臺大學術典藏 |
2018-09-10T07:42:57Z |
A 1.7-mW, 16.8% Frequency Tuning, 24-GHz Transformer-Based LC-VCO using 0.18-um CMOS Technology
|
Yen-Hung Kuo;Jeng-Han Tsai;Tian-Wei Huang; Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang; TIAN-WEI HUANG |
| 義守大學 |
2017-09 |
行動社群訊息中文字與表情貼圖使用模式之研究-以LINE為例
|
郭彥宏; Yen-Hung Kuo |
| 國立臺灣師範大學 |
2014-10-30T09:28:46Z |
A 1.7-mW, 14.4% Frequency Tuning,24GHz VCO with Current-Reused Structure Using 0.18-μm CMOS Technology
|
Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang |
| 國立臺灣師範大學 |
2014-10-30T09:28:45Z |
A V-band VCO using fT-doubling technique in 0.18-μm CMOS
|
Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang; Huei Wang |
| 國立臺灣師範大學 |
2014-10-30T09:28:45Z |
An ultra low-power 24 GHz phase-lock-loop with low phase-noise VCO embedded in 0.18-μm CMOS process
|
Yu-Hsuan Lin; Jeng-Han Tsai; Yen-Hung Kuo; Tian-Wei Huang |
| 國立臺灣師範大學 |
2014-10-30T09:28:45Z |
A 24-GHz 3.8-dB NF Low-Noise Amplifier with Built-In Linearizer
|
Yen-Hung Kuo; Jeng-Han Tsai; Wei-Hung Chou; Tian-Wei Huang |
| 國立臺灣師範大學 |
2014-10-30T09:28:45Z |
Admittance-Transforming Injection-Locked Frequency Divider and Low-Supply-Voltage Current Mode Logic Divider
|
Yen-Hung Kuo; Jeng-Han Tsai; Wei-Hung Chou; Tian-Wei Huang |
| 國立臺灣師範大學 |
2014-10-30T09:28:45Z |
A 1.5-mW, 23.6% frequency locking range,24-GHz injection-locked frequency divider
|
Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang |
| 國立臺灣師範大學 |
2014-10-30T09:28:45Z |
A 24-GHz 3.8-dB NF Low-Noise Amplifier with Built-In Linearizer
|
Yen-Hung Kuo; Jeng-Han Tsai; Wei-Hung Chou; Tian-Wei Huang |
| 國立臺灣師範大學 |
2014-10-30T09:28:45Z |
A 1.5-mW, 23.6% frequency locking range,24-GHz injection-locked frequency divider
|
Yen-Hung Kuo; Jeng-Han Tsai; Tian-Wei Huang |
| 國立臺灣師範大學 |
2014-10-30T09:28:43Z |
Design and analysis of a 77.3% locking-range divide-by-4 frequency divider
|
Yen-Hung Kuo; Jeng-Han Tsai; Hong-Yeh Chang; Tian-Wei Huang |
| 國立臺灣師範大學 |
2014-10-30T09:28:43Z |
Design and analysis of a 77.3% locking-range divide-by-4 frequency divider
|
Tian-Wei Huang; Yen-Hung Kuo; Jeng-Han Tsai; Hong-Yeh Chang |
| 國立臺灣師範大學 |
2011-12-08 |
An ultra low-power 24 GHz phase-lock-loop with low phase-noise VCO embedded in 0.18-μm CMOS process
|
Yu-Hsuan Lin; Jeng-Han Tsai; Yen-Hung Kuo; Tian-Wei Huang |
| 元智大學 |
2009-06 |
A 1.7-mW, 14.4% Frequency Tuning, 24GHz VCO with Current-Reused Structure Using 0.18-um CMOS Technology
|
蔡政翰; Yen-Hung Kuo; Tian-Wei Huang |
| 元智大學 |
2009-06 |
A 1.7-mW, 14.4% Frequency Tuning, 24GHz VCO with Current-Reused Structure Using 0.18-um CMOS Technology
|
蔡政翰; Yen-Hung Kuo; Tian-Wei Huang |
| 中原大學 |
2008-06-23 |
國內總體經濟因素對共同基金影響之研究
|
郭彥宏; Yen-Hung Kuo |
| 南台科技大學 |
2006 |
J2EE平台下具擴充性工作流程管理系統建置
|
郭彥宏; Yen-Hung Kuo |
