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Showing items 41-50 of 80 (8 Page(s) Totally)
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| 國立交通大學 |
2019-04-02T05:58:16Z |
A framework for self-regulated digital learning (SRDL)
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Yen, M. -H.; Chen, S.; Wang, C. -Y.; Chen, H. -L.; Hsu, Y. -S.; Liu, T. -C. |
| 臺大學術典藏 |
2018-09-10T09:22:15Z |
Design of a low-power OFDM baseband receiver for wireless communications
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Sung, C.-H.; Yen, M.-H.; Chen, S.-J.; SAO-JIE CHEN; Kuo, C.-H.; Yu, C. |
| 臺大學術典藏 |
2018-09-10T09:22:15Z |
Design and implementation of a low-power OFDM receiver for wireless communications
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Yu, C.; Sung, C.-H.; Kuo, C.-H.; Yen, M.-H.; Chen, S.-J.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T08:42:21Z |
A three-sided rearrangeable switching network for a binary fat tree
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Yen, M.-H.;Yu, C.;Shin, H.-Y.;Chen, S.-J.; Yen, M.-H.; Yu, C.; Shin, H.-Y.; Chen, S.-J.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T08:42:21Z |
A novel low-power 64-point pipelined FFT/IFFT processor for OFDM applications
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Yu, C.;Liao, Y.-T.;Yen, M.-H.;Hsiung, P.-A.;Chen, S.-J.; Yu, C.; Liao, Y.-T.; Yen, M.-H.; Hsiung, P.-A.; Chen, S.-J.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T08:42:21Z |
A low-power 64-point pipeline FFT/IFFT processor for OFDM applications
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Yu, C.;Yen, M.-H.;Hsiung, P.-A.;Chen, S.-J.; Yu, C.; Yen, M.-H.; Hsiung, P.-A.; Chen, S.-J.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T08:14:42Z |
Design of a low power Viterbi decoder for wireless communication applications
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Chen, C.-J.;Yu, C.;Yen, M.-H.;Hsiung, P.-A.;Chen, S.-J.; Chen, C.-J.; Yu, C.; Yen, M.-H.; Hsiung, P.-A.; Chen, S.-J.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T08:14:42Z |
ARAL-CR: An adaptive reasoning and learning cognitive radio platform
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Chen, S.-J.;Hsiung, P.-A.;Yu, C.;Yen, M.-H.;Sezer, S.;Schulte, M.;Hu, Y.-H.; Chen, S.-J.; Hsiung, P.-A.; Yu, C.; Yen, M.-H.; Sezer, S.; Schulte, M.; Hu, Y.-H.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T07:36:34Z |
A 900 MHz to 5.2 GHz dual-loop feedback multi-band LNA
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Lin, J.-W.;Yen, D.-T.;Hu, W.-Y.;Chu, Y.;Yen, M.-H.;Hsiung, P.-A.;Chen, S.-J.; Lin, J.-W.; Yen, D.-T.; Hu, W.-Y.; Chu, Y.; Yen, M.-H.; Hsiung, P.-A.; Chen, S.-J.; SAO-JIE CHEN |
| 臺大學術典藏 |
2018-09-10T07:36:33Z |
Parallel implementation of convolution encoder for software defined radio on DSP architecture
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SAO-JIE CHEN; Hu, Y.H.; Lin, J.-C.;Yu, C.;Yen, M.-H.;Hsiung, P.-A.;Chen, S.-J.;Hu, Y.H.; Lin, J.-C.; Yu, C.; Yen, M.-H.; Hsiung, P.-A.; Chen, S.-J. |
Showing items 41-50 of 80 (8 Page(s) Totally)
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