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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"yeo jih chiang"的相關文件
顯示項目 1-7 / 7 (共1頁)
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| 國立臺灣大學 |
2006 |
Area-Efficient VLSI Design of Reed-Solomon Decoder for 10GBase-LX4 Optical Communication Systems
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Hsu, Huai-Yi; Wu, An-Yeu (Andy); Yeo, Jih-Chiang |
| 國立臺灣大學 |
2006 |
Multi-Symbol-Sliced Dynamically Reconfigurable Reed–Solomon Decoder Design Based on Unified Finite-Field Processing Element
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Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu |
| 國立臺灣大學 |
2005 |
以統一式有限場處理單元為基礎的可動態重規劃之里德所羅門解碼器矽智財設計
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游志強; Yeo, Jih-Chiang |
| 國立臺灣大學 |
2004-08 |
Area-efficient VLSI design of Reed-Solomon decoder for 10GBase-LX4 optical communication systems
|
Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu |
| 臺大學術典藏 |
2004-08 |
Area-efficient VLSI design of Reed-Solomon decoder for 10GBase-LX4 optical communication systems
|
Hsu, H.-Y. and Yeo, J.-C. and Wu, A.-Y.; Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu; Hsu, Huai-Yi; Yeo, Jih-Chiang; Wu, An-Yeu |
| 國立臺灣大學 |
2004 |
A scalable Reed-Solomon decoding processor based on unified finite-field processing element design
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Yeo, Jih-Chiang; Hsu, Huai-Yi; Wu, An-Yeu |
| 臺大學術典藏 |
2004 |
A scalable Reed-Solomon decoding processor based on unified finite-field processing element design
|
Yeo, Jih-Chiang; Hsu, Huai-Yi; Wu, An-Yeu; Yeo, Jih-Chiang; Hsu, Huai-Yi; Wu, An-Yeu |
顯示項目 1-7 / 7 (共1頁)
1
每頁顯示[10|25|50]項目
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