臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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机构	日期	题名	作者
臺大學術典藏	2019-10-24T07:45:21Z	Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits	江介宏;JIE-HONG JIANG;Jie-Hong R. Jiang;Yi-Hsiang Lai;Hao-Yuan Kuo;Nian-Ze Lee; Nian-Ze Lee; Hao-Yuan Kuo; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG; 江介宏
臺大學術典藏	2019-10-24T07:45:21Z	Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits	江介宏;JIE-HONG JIANG;Jie-Hong R. Jiang;Yi-Hsiang Lai;Hao-Yuan Kuo;Nian-Ze Lee; Nian-Ze Lee; Hao-Yuan Kuo; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG; 江介宏
臺大學術典藏	2019-10-24T07:43:07Z	Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits	JIE-HONG JIANG;Jie-Hong R. Jiang;Yi-Hsiang Lai;Hao-Yuan Kuo;Nian-Ze Lee; Nian-Ze Lee; Hao-Yuan Kuo; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏	2019-10-24T07:43:07Z	Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits	JIE-HONG JIANG;Jie-Hong R. Jiang;Yi-Hsiang Lai;Hao-Yuan Kuo;Nian-Ze Lee; Nian-Ze Lee; Hao-Yuan Kuo; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏	2018-09-10T15:26:17Z	A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines	Yi-Hsiang Lai;Chi-Chuan Chuang;Jie-Hong R. Jiang; Yi-Hsiang Lai; Chi-Chuan Chuang; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏	2018-09-10T15:26:17Z	A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines	Yi-Hsiang Lai;Chi-Chuan Chuang;Jie-Hong R. Jiang; Yi-Hsiang Lai; Chi-Chuan Chuang; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏	2018-09-10T15:26:17Z	SPOCK: Static performance analysis and deadlock verification for efficient asynchronous circuit synthesis	Chun-Hong Shih;Yi-Hsiang Lai;Jie-Hong R. Jiang; Chun-Hong Shih; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏	2018-09-10T15:26:17Z	SPOCK: Static performance analysis and deadlock verification for efficient asynchronous circuit synthesis	Chun-Hong Shih;Yi-Hsiang Lai;Jie-Hong R. Jiang; Chun-Hong Shih; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏	2018-09-10T15:26:17Z	Asynchronous QDI Circuit Synthesis from Signal Transition Protocols	Bo-Yuan Huang;Yi-Hsiang Lai;Jie-Hong R. Jiang; Bo-Yuan Huang; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏	2018-09-10T15:26:17Z	Asynchronous QDI Circuit Synthesis from Signal Transition Protocols	Bo-Yuan Huang;Yi-Hsiang Lai;Jie-Hong R. Jiang; Bo-Yuan Huang; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏	2018-09-10T15:00:43Z	Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits	Chi-Chuan Chuang;Yi-Hsiang Lai;Jie-Hong R. Jiang; Chi-Chuan Chuang; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG
臺大學術典藏	2018-09-10T15:00:43Z	Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits	Chi-Chuan Chuang;Yi-Hsiang Lai;Jie-Hong R. Jiang; Chi-Chuan Chuang; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG

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